SYSRST_CTRL Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 4.760s 2.111ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 5.230s 2.453ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.800s 2.196ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.710s 2.305ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 8.630s 4.025ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 4.150s 2.039ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 17.310s 39.200ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 4.500s 3.334ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.750s 2.045ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 4.150s 2.039ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.500s 3.334ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 19.020s 137.936ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 40.040s 76.801ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.020s 3.197ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 3.630s 3.357ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.300s 2.512ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 1.200s 2.255ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 1.940s 5.058ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 5.030s 2.613ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.730s 2.545ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 17.290s 39.665ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 15.550s 7.117ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 4.210s 2.015ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.610s 2.017ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.540s 2.284ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.540s 2.284ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 8.630s 4.025ms 1 1 100.00
sysrst_ctrl_csr_rw 4.150s 2.039ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.500s 3.334ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.770s 8.722ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 8.630s 4.025ms 1 1 100.00
sysrst_ctrl_csr_rw 4.150s 2.039ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.500s 3.334ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 9.770s 8.722ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 10.960s 22.326ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.399m 42.399ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.399m 42.399ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 8.480s 7.516ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00