UART Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: e649bd3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.050s	310.307us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.580s	25.993us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.580s	151.012us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.850s	179.159us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.640s	25.054us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.750s	23.983us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.580s	151.012us	1	1	100.00
		uart_csr_aliasing	0.640s	25.054us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	11.380s	42.009ms	1	1	100.00
V2	parity	uart_smoke	1.050s	310.307us	1	1	100.00
		uart_tx_rx	11.380s	42.009ms	1	1	100.00
V2	parity_error	uart_intr	14.890s	22.943ms	1	1	100.00
		uart_rx_parity_err	1.958m	104.590ms	1	1	100.00
V2	watermark	uart_tx_rx	11.380s	42.009ms	1	1	100.00
		uart_intr	14.890s	22.943ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.014m	48.882ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	2.885m	134.265ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	18.580s	71.993ms	1	1	100.00
V2	rx_frame_err	uart_intr	14.890s	22.943ms	1	1	100.00
V2	rx_break_err	uart_intr	14.890s	22.943ms	1	1	100.00
V2	rx_timeout	uart_intr	14.890s	22.943ms	1	1	100.00
V2	perf	uart_perf	7.431m	14.574ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.740s	5.399ms	1	1	100.00
V2	line_loopback	uart_loopback	6.740s	5.399ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	18.550s	203.519ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.850s	1.919ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.660s	7.346ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	35.130s	6.180ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.653m	69.606ms	1	1	100.00
V2	stress_all	uart_stress_all	8.535m	112.326ms	1	1	100.00
V2	alert_test	uart_alert_test	0.710s	12.647us	1	1	100.00
V2	intr_test	uart_intr_test	0.640s	73.061us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.790s	118.142us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.790s	118.142us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.580s	25.993us	1	1	100.00
		uart_csr_rw	0.580s	151.012us	1	1	100.00
		uart_csr_aliasing	0.640s	25.054us	1	1	100.00
		uart_same_csr_outstanding	0.630s	41.064us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.580s	25.993us	1	1	100.00
		uart_csr_rw	0.580s	151.012us	1	1	100.00
		uart_csr_aliasing	0.640s	25.054us	1	1	100.00
		uart_same_csr_outstanding	0.630s	41.064us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.900s	41.243us	1	1	100.00
		uart_tl_intg_err	0.950s	60.531us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.950s	60.531us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.190s	2.912ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.106427893141454667275416519195446093902339370642003465992571045045566116183873
      Line 79, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 203014697396 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 203014697396 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 203022447396 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 203022447396 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 203498697396 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.36892088096223534450803461777045762988054851390699196068483526860752700910457
      Line 180, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2683255882 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 2683255882 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2683255882 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 2686445882 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 6
        UVM_ERROR @ 2686455882 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty