CHIP Simulation Results

Thursday September 04 2025 19:17:11 UTC

GitHub Revision: `e649bd3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.984m	2.974ms	1	1	100.00
		chip_sw_example_rom	1.129m	2.123ms	1	1	100.00
		chip_sw_example_manufacturer	1.733m	2.553ms	1	1	100.00
		chip_sw_example_concurrency	2.562m	3.337ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.516m	6.656ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.642m	5.294ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.002m	3.883ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.036h	30.354ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	41.490s	1.715ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.036h	30.354ms	1	1	100.00
		chip_csr_rw	6.642m	5.294ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.170s	215.861us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.093m	4.040ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.093m	4.040ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.093m	4.040ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.831m	4.442ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.831m	4.442ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.930m	4.472ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.284m	4.465ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.376m	4.498ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.375m	8.306ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.781m	8.698ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.569m	4.281ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.620m	5.356ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.620m	5.356ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.150m	2.988ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.961m	3.042ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.161m	3.788ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.439m	4.356ms	1	1	100.00
		chip_tap_straps_testunlock0	9.963m	9.312ms	1	1	100.00
		chip_tap_straps_rma	6.806m	7.334ms	1	1	100.00
		chip_tap_straps_prod	15.006m	14.310ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.775m	2.776ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.675m	9.188ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	8.327m	5.089ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	8.327m	5.089ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.555m	7.899ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	17.502m	12.568ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.141m	4.585ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.912m	6.307ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.848m	18.225ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.468m	2.701ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.369m	6.710ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.706m	2.862ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.328m	9.235ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.132m	3.069ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.307m	5.173ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.684m	2.024ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.874m	3.032ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.619m	5.253ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.051m	5.423ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.852m	3.185ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.051m	5.423ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.908m	2.862ms	1	1	100.00
		chip_sw_aes_smoketest	2.554m	2.606ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.677m	2.662ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.456m	2.883ms	1	1	100.00
		chip_sw_csrng_smoketest	2.374m	3.036ms	1	1	100.00
		chip_sw_entropy_src_smoketest	11.084m	6.273ms	1	1	100.00
		chip_sw_gpio_smoketest	2.593m	3.587ms	1	1	100.00
		chip_sw_hmac_smoketest	3.654m	3.592ms	1	1	100.00
		chip_sw_kmac_smoketest	3.229m	3.519ms	1	1	100.00
		chip_sw_otbn_smoketest	10.452m	6.049ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.886m	6.358ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.586m	5.345ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.546m	2.646ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.432m	2.942ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.863m	3.374ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.571m	3.067ms	1	1	100.00
		chip_sw_uart_smoketest	2.484m	3.428ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.813m	2.873ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.534m	5.010ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.160h	59.585ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.989m	14.942ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	1.980m	4.081ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.078m	3.211ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.836m	3.229ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.835h	54.840ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.997h	57.745ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	45.920s	2.821ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	45.920s	2.821ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.036h	30.354ms	1	1	100.00
		chip_same_csr_outstanding	28.692m	15.873ms	1	1	100.00
		chip_csr_hw_reset	3.516m	6.656ms	1	1	100.00
		chip_csr_rw	6.642m	5.294ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.036h	30.354ms	1	1	100.00
		chip_same_csr_outstanding	28.692m	15.873ms	1	1	100.00
		chip_csr_hw_reset	3.516m	6.656ms	1	1	100.00
		chip_csr_rw	6.642m	5.294ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	9.190s	348.353us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.890s	48.496us	1	1	100.00
		xbar_smoke_large_delays	59.270s	9.748ms	1	1	100.00
		xbar_smoke_slow_rsp	55.480s	6.337ms	1	1	100.00
		xbar_random_zero_delays	17.520s	206.905us	1	1	100.00
		xbar_random_large_delays	3.414m	34.075ms	1	1	100.00
		xbar_random_slow_rsp	1.471m	10.351ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	23.380s	790.609us	1	1	100.00
		xbar_error_and_unmapped_addr	19.950s	887.967us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	23.350s	428.596us	1	1	100.00
		xbar_error_and_unmapped_addr	19.950s	887.967us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	13.360s	537.840us	1	1	100.00
		xbar_access_same_device_slow_rsp	4.403m	30.144ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	23.080s	406.752us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.188m	15.158ms	1	1	100.00
		xbar_stress_all_with_error	1.635m	2.158ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	57.350s	151.436us	1	1	100.00
		xbar_stress_all_with_reset_error	1.590m	389.149us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.989m	14.942ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.876m	30.565ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.319m	15.491ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.943m	10.824ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.496m	16.098ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.010m	16.041ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.079m	19.573ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.341m	15.326ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.230s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.030s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	21.520s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.990s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	19.110s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	20.900s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	21.900s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.210s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.460s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	19.530s	10.320us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.640s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.980s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.350s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.730s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.730s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.440s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.760s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.260s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.150s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.440s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.320s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.040s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.070s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	21.020s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	21.020s	10.180us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.995m	15.344ms	1	1	100.00
		rom_e2e_asm_init_dev	39.059m	15.615ms	1	1	100.00
		rom_e2e_asm_init_prod	38.673m	15.443ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.819m	15.607ms	1	1	100.00
		rom_e2e_asm_init_rma	40.442m	14.882ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.567m	15.546ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.212m	14.560ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.815m	15.365ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.075m	15.337ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.602m	34.815ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.602m	34.815ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.259m	2.946ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.468m	2.701ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.165m	3.287ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.847m	3.210ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.988m	7.746ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.692m	2.623ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.010m	5.385ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	7.304m	6.131ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.179m	5.539ms	1	1	100.00
		chip_plic_all_irqs_10	5.109m	3.829ms	1	1	100.00
		chip_plic_all_irqs_20	6.324m	4.275ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.748m	2.880ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	19.822m	15.608ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.154m	3.515ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.308m	2.758ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.531m	11.668ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.918m	8.160ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.058m	6.328ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.652m	7.802ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.362h	254.746ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.526m	4.446ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.886m	6.358ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.526m	4.446ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.942m	8.896ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.942m	8.896ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.246m	6.492ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.525m	5.129ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.626m	6.345ms	1	1	100.00
		chip_sw_aes_idle	2.847m	3.210ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.748m	3.682ms	1	1	100.00
		chip_sw_kmac_idle	1.804m	2.993ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.334m	4.838ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.272m	4.568ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.616m	4.290ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.732m	4.226ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	15.397m	11.780ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.894m	3.686ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.312m	4.519ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.648m	3.532ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.576m	4.291ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.942m	4.907ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.163m	4.139ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.555m	7.899ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.514m	6.677ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.648m	3.532ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.576m	4.291ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.141m	4.585ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.912m	6.307ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.848m	18.225ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.468m	2.701ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.369m	6.710ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.706m	2.862ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.328m	9.235ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.132m	3.069ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.307m	5.173ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.684m	2.024ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.119m	2.562ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.983m	4.921ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.160m	7.114ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.789m	24.485ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.461m	2.822ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.243m	3.114ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	17.851m	11.309ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.418m	2.846ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.398m	3.968ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.816m	25.154ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.638h	120.429ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.555m	7.899ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.154m	4.223ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.492m	3.573ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	7.304m	6.131ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.918m	8.160ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.354m	8.576ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.166m	4.674ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.859m	5.614ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.871m	2.382ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	36.295m	13.184ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.591m	2.992ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.522m	7.607ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.591m	2.992ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.354m	8.576ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.895m	2.809ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.558m	21.055ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.310m	6.084ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.912m	6.307ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.704m	4.000ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.141m	4.585ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	57.501m	44.469ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.558m	21.055ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.002m	2.818ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	14.753m	6.990ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.617m	5.117ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	57.501m	44.469ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.617m	5.117ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.617m	5.117ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.617m	5.117ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.617m	5.117ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	7.304m	6.131ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.260m	3.486ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.595m	4.480ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.545m	5.122ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.545m	5.122ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.628m	3.284ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.706m	2.862ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.748m	3.682ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.532m	2.840ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.721m	3.935ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.026m	5.798ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.851m	5.080ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.365m	4.350ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.846m	4.039ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	14.753m	6.990ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.328m	9.235ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	21.096m	10.417ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.988m	7.746ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	31.970m	11.820ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.163m	2.333ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.295m	2.827ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.132m	3.069ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	14.753m	6.990ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.860m	2.558ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	17.744m	8.604ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.804m	2.993ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.010m	5.385ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.439m	4.356ms	1	1	100.00
		chip_tap_straps_rma	6.806m	7.334ms	1	1	100.00
		chip_tap_straps_prod	15.006m	14.310ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.292m	3.265ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	12.229m	7.984ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.617m	5.117ms	1	1	100.00
		chip_sw_flash_rma_unlocked	57.501m	44.469ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.526m	3.250ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.893m	6.940ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.344m	7.801ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.365m	7.446ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.753m	6.990ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.655m	8.954ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.831m	8.544ms	1	1	100.00
		chip_prim_tl_access	1.260m	3.486ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.514m	6.677ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.894m	3.686ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.312m	4.519ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.648m	3.532ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.576m	4.291ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.942m	4.907ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.163m	4.139ms	1	1	100.00
		chip_tap_straps_dev	3.439m	4.356ms	1	1	100.00
		chip_tap_straps_rma	6.806m	7.334ms	1	1	100.00
		chip_tap_straps_prod	15.006m	14.310ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.069m	9.694ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.621m	3.274ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.370m	3.333ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.500m	2.971ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.753m	3.624ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.895m	26.086ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.069m	9.694ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.098h	49.857ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.029h	50.430ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.840m	10.672ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.087h	44.507ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.895m	26.086ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.294m	2.328ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.170m	2.906ms	1	1	100.00
		rom_volatile_raw_unlock	57.590s	2.221ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.077m	17.610ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.848m	18.225ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.626m	6.345ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.626m	6.345ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.626m	6.345ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.129m	3.227ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.558m	21.055ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.129m	3.227ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.753m	6.990ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.865m	5.230ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.793m	2.350ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.558m	21.055ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.129m	3.227ms	1	1	100.00
		chip_sw_keymgr_key_derivation	14.753m	6.990ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.865m	5.230ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.793m	2.350ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.098m	4.907ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.292m	3.265ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.526m	3.250ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.893m	6.940ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.344m	7.801ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.365m	7.446ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.511m	13.299ms	1	1	100.00
		chip_prim_tl_access	1.260m	3.486ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.260m	3.486ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	19.928m	8.521ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.775m	7.158ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.991m	27.318ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.522m	7.196ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.405m	6.500ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.251m	6.861ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.387m	24.583ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.414m	14.395ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.942m	8.896ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.591m	11.840ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.513m	4.427ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.775m	7.158ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.453m	3.907ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	33.587m	31.346ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.777m	6.667ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.214m	5.960ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.917m	26.594ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.907m	7.420ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.536m	9.744ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.682m	25.637ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.194m	3.223ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	7.304m	6.131ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.655m	8.954ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.655m	8.954ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.536m	9.744ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.917m	26.594ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.513m	4.427ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.886m	6.358ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.800m	4.698ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.796m	4.066ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.435m	4.102ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	19.822m	15.608ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.675m	2.815ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	7.304m	6.131ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.058m	6.328ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.197m	4.993ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.390m	4.819ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.167m	2.993ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.793m	2.350ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.796m	4.066ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.796m	4.066ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	8.301m	9.053ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.405m	13.345ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.800m	4.698ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.113m	5.126ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.710m	5.546ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.806m	7.334ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.069m	9.694ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.179m	5.539ms	1	1	100.00
		chip_plic_all_irqs_10	5.109m	3.829ms	1	1	100.00
		chip_plic_all_irqs_20	6.324m	4.275ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.377m	2.570ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.986m	2.724ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.989m	14.942ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.259m	6.306ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.244m	3.542ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.298m	3.541ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.108m	3.233ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.865m	5.230ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.307m	5.173ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.454m	8.022ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	8.155m	9.213ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.831m	8.544ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	7.304m	6.131ms	1	1	100.00
		chip_sw_data_integrity_escalation	8.327m	5.089ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.907m	7.420ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.634m	22.710ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.449m	2.649ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.529m	3.672ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.824m	4.040ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.634m	22.710ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.634m	22.710ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.877m	21.024ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.877m	21.024ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.427m	6.027ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	52.602m	34.815ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.698m	2.954ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.156m	3.318ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.413m	3.876ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.460m	4.265ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.411m	7.538ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.396h	31.434ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.640m	11.736ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.163m	2.356ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.605m	2.962ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.749m	2.911ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.593h	71.664ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.570m	3.936ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	3.046m	4.644ms	0	1	0.00
		rom_e2e_jtag_debug_dev	10.079m	13.236ms	0	1	0.00
		rom_e2e_jtag_debug_rma	18.995m	12.602ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.891m	2.942ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.376m	4.054ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.511m	4.874ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.100s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.518m	5.116ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.713m	2.919ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.257m	5.832ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.298m	7.459ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.288m	2.512ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.168m	5.270ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.926m	2.497ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.503m	5.614ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.646m	5.987ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.155m	4.559ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.536m	9.744ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	3.046m	4.644ms	0	1	0.00
		rom_e2e_jtag_debug_dev	10.079m	13.236ms	0	1	0.00
		rom_e2e_jtag_debug_rma	18.995m	12.602ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.673m	4.801ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	7.304m	6.131ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.443h	37.700ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.443h	37.700ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	1.944m	3.069ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.831m	4.442ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.347m	18.389ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.342m	2.883ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.926m	5.028ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.626m	2.539ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.715m	2.400ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.271m	3.483ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.716s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.607m	2.922ms	1	1	100.00
		TOTAL			282	325	86.77

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.115013883921324845673057915458693138619583961717966548354355472719452369002628
    Line 537, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.14552343378857354266778515713863248963484272748120366574570576677576519029152
    Line 527, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.22817403512748435137582871954265516945333418251619323509524139421035934523421
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.63640973382278627112885014540512027248418452298113642161589666122225439298980
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.84555285122309938186082407844168207526097604261736926812014337253516298312636
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.96606654638589641180000403911908590872854197058346451223275129451533583103235
    Line 549, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.28049758311453298780208719647615569223619196291095600272284201909721483530667
    Line 540, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1364503972607830896329090942523267634214775493564677409732207998877566394951
    Line 543, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.80513740029529022799552523048934499975484365998156056733706407284955718197355
    Line 557, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.51070097028858204841922350581934847801666880854347024735945155956048588799633
    Line 547, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.67520769619894312521409456318908411748496665251758772166346304495410051759509
    Line 483, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.75417115201984355825438543965194860903941912049995734503084101636636305683192
    Line 524, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.101029893320270860587277631031281933178824304501879133702680603608279174021775
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.89481402495822434568204795852389426779412715190499639389098156625869322315039
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.158s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.8577835684386690927891478289964473938445920193104092611849658539999893649334
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.239s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.71165878461738938904429379072328549568039507656603845652494818318264203388229
    Line 589, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.97972532506701299207350556881603372401477500293581272351202954906443033022559
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.14879613226599199690684539093793785423353349086051337494216974523417380802819
    Line 574, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.49388137368047703586435323686564034504298479525138170671203792831798646628262
    Line 547, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.8029128278694230548318528047939897676268167135660517643886522020599725963515
    Line 580, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2988.440000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2988.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.113133317053932148253847331974217288207645028939259287834830946725876951411123
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3542.280001 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3542.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111124) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.19701010976349099887851835622881902561639067376563299461777455420955508367555
Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4066.494570 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111124) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4066.494570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.103918482845439666933847305212991895680561708122909950416516791811784811271110
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34814.708615 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34814.708615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.70708604281556546169865189162722484993139779538905508896246401068180724526206
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2623.356000 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2623.356000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.43509640215503863754118178595154481800269319311474280095528991382626164441584
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2757.771975 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2757.771975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.35051631033659773120922335110966175761036483783560942787636865751654101463822
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2840.327883 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2840.327883 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33534) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.68873824764156653859280144883888171668020200362337900658017294938679380093480
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2821.280016 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33534) { a_addr: 'h1036c  a_data: 'hcddc9244  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1a2a1  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2821.280016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.83692339648988779067481083570950584621821458249135597636273626179646371033788
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2911.449660 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2911.449660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.112665854090748055170909162466220723478680793994174195441496339465247596324534
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3211.407500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3211.407500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.5245037418808432900567078201715356552253831596487214288607312788183139335774
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3229.330000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3229.330000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.2272514989303869260961459803497754840825557618614940260344814690933525728508
    Line 413, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 12567.585160 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 12567.585160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.8817759357501296123339429678684125833473614589958799596059158604423528535253
    Line 444, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3935.863240 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3935.863240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.52596217399843490631204364993499081101028420324637644644928080183918861340334
    Line 544, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.57829560535849198940689162729219880694066951995594854123754039139928390024354
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.81871421639501160579382901081795892118211652889604112913817146850773652009149
    Line 463, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 4644.488348 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4644.488348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.71046236291516719432841615285357297752626574691180479325440411770242461929068
    Line 444, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 13236.138850 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 13236.138850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32456) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.112695176436908388683101244601371108943813413750850167829001047575108788052265
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1715.094520 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32456) { a_addr: 'h10684  a_data: 'hb27d5f73  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h1a2c7  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1715.094520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---