83a1436| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 6.280s | 5.883ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 1.610s | 1.142ms | 1 | 1 | 100.00 |
| V1 | csr_rw | adc_ctrl_csr_rw | 1.420s | 421.154us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 32.840s | 26.389ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 2.140s | 2.136ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 1.280s | 416.910us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 1.420s | 421.154us | 1 | 1 | 100.00 |
| adc_ctrl_csr_aliasing | 2.140s | 2.136ms | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 1.288m | 167.863ms | 1 | 1 | 100.00 |
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 2.975m | 162.085ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 3.778m | 485.278ms | 1 | 1 | 100.00 |
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 1.272m | 166.844ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 3.468m | 536.913ms | 1 | 1 | 100.00 |
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 8.626m | 604.151ms | 1 | 1 | 100.00 |
| V2 | filters_both | adc_ctrl_filters_both | 8.599m | 600.000ms | 0 | 1 | 0.00 |
| V2 | clock_gating | adc_ctrl_clock_gating | 1.230s | 15.864ms | 0 | 1 | 0.00 |
| V2 | poweron_counter | adc_ctrl_poweron_counter | 8.270s | 3.772ms | 1 | 1 | 100.00 |
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 17.350s | 40.176ms | 1 | 1 | 100.00 |
| V2 | fsm_reset | adc_ctrl_fsm_reset | 1.943m | 68.720ms | 1 | 1 | 100.00 |
| V2 | stress_all | adc_ctrl_stress_all | 3.186m | 437.295ms | 1 | 1 | 100.00 |
| V2 | alert_test | adc_ctrl_alert_test | 1.090s | 354.163us | 1 | 1 | 100.00 |
| V2 | intr_test | adc_ctrl_intr_test | 1.670s | 537.678us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 2.640s | 544.659us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 2.640s | 544.659us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 1.610s | 1.142ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 1.420s | 421.154us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 2.140s | 2.136ms | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 10.390s | 2.542ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 1.610s | 1.142ms | 1 | 1 | 100.00 |
| adc_ctrl_csr_rw | 1.420s | 421.154us | 1 | 1 | 100.00 | ||
| adc_ctrl_csr_aliasing | 2.140s | 2.136ms | 1 | 1 | 100.00 | ||
| adc_ctrl_same_csr_outstanding | 10.390s | 2.542ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 14 | 16 | 87.50 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 4.700s | 7.931ms | 1 | 1 | 100.00 |
| adc_ctrl_tl_intg_err | 9.640s | 4.374ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 9.640s | 4.374ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 7.700s | 70.769ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 23 | 25 | 92.00 |
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
0.adc_ctrl_clock_gating.39381600198631702925976578546309020295837276176202471879914299380185113882570
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log
UVM_ERROR @ 15864103129 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 15864103129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.adc_ctrl_filters_both.43452279921416064870896235583847693213727154203301961724485231827372817487158
Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---