| V1 |
smoke |
aon_timer_smoke |
1.530s |
675.634us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
1.440s |
1.193ms |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
0.800s |
342.975us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
9.420s |
7.136ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
1.240s |
504.519us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
0.940s |
536.025us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
0.800s |
342.975us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.240s |
504.519us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
0.800s |
373.832us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
1.070s |
511.994us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
11.230s |
30.682ms |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
2.400s |
696.000us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
7.390s |
4.116ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
0.860s |
505.351us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
1.810s |
504.007us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
1.870s |
465.628us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
1.870s |
465.628us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
1.440s |
1.193ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.800s |
342.975us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.240s |
504.519us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.080s |
1.113ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
1.440s |
1.193ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.800s |
342.975us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.240s |
504.519us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
1.080s |
1.113ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
3.590s |
4.148ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
6.250s |
8.775ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
6.250s |
8.775ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
1.410s |
535.793us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
0.840s |
851.125us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
7.340s |
3.921ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
0.890s |
584.944us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
1.820s |
4.479ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
17.670s |
4.116ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |