EDN Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.930s	45.753us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.890s	57.732us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.710s	25.396us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.700s	700.378us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.950s	25.877us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.840s	27.222us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.710s	25.396us	1	1	100.00
		edn_csr_aliasing	0.950s	25.877us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.400s	264.934us	1	1	100.00
V2	csrng_commands	edn_genbits	1.400s	264.934us	1	1	100.00
V2	genbits	edn_genbits	1.400s	264.934us	1	1	100.00
V2	interrupts	edn_intr	0.810s	42.257us	1	1	100.00
V2	alerts	edn_alert	1.030s	45.456us	1	1	100.00
V2	errs	edn_err	1.200s	32.274us	1	1	100.00
V2	disable	edn_disable	0.820s	23.542us	1	1	100.00
		edn_disable_auto_req_mode	0.880s	32.811us	1	1	100.00
V2	stress_all	edn_stress_all	0.920s	42.904us	1	1	100.00
V2	intr_test	edn_intr_test	0.970s	14.469us	1	1	100.00
V2	alert_test	edn_alert_test	0.980s	114.505us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.880s	33.665us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.880s	33.665us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.890s	57.732us	1	1	100.00
		edn_csr_rw	0.710s	25.396us	1	1	100.00
		edn_csr_aliasing	0.950s	25.877us	1	1	100.00
		edn_same_csr_outstanding	1.070s	113.934us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.890s	57.732us	1	1	100.00
		edn_csr_rw	0.710s	25.396us	1	1	100.00
		edn_csr_aliasing	0.950s	25.877us	1	1	100.00
		edn_same_csr_outstanding	1.070s	113.934us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.360s	240.000us	1	1	100.00
		edn_tl_intg_err	1.770s	69.616us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.990s	30.481us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.030s	45.456us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.360s	240.000us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.360s	240.000us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.360s	240.000us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.360s	240.000us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.030s	45.456us	1	1	100.00
		edn_sec_cm	3.360s	240.000us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.030s	45.456us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.770s	69.616us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	39.580s	15.843ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00