HMAC Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.290s 421.931us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.680s 36.537us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.950s 73.487us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 6.810s 401.115us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.410s 1.198ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.850s 31.292us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.950s 73.487us 1 1 100.00
hmac_csr_aliasing 5.410s 1.198ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 36.520s 9.108ms 1 1 100.00
V2 back_pressure hmac_back_pressure 25.780s 1.332ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.750s 189.275us 1 1 100.00
hmac_test_sha384_vectors 4.947m 13.992ms 1 1 100.00
hmac_test_sha512_vectors 18.840s 223.366us 1 1 100.00
hmac_test_hmac256_vectors 9.110s 310.729us 1 1 100.00
hmac_test_hmac384_vectors 5.440s 187.770us 1 1 100.00
hmac_test_hmac512_vectors 7.550s 671.761us 1 1 100.00
V2 burst_wr hmac_burst_wr 8.700s 449.287us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 9.972m 26.416ms 1 1 100.00
V2 error hmac_error 1.109m 1.587ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 25.650s 683.244us 1 1 100.00
V2 save_and_restore hmac_smoke 10.290s 421.931us 1 1 100.00
hmac_long_msg 36.520s 9.108ms 1 1 100.00
hmac_back_pressure 25.780s 1.332ms 1 1 100.00
hmac_datapath_stress 9.972m 26.416ms 1 1 100.00
hmac_burst_wr 8.700s 449.287us 1 1 100.00
hmac_stress_all 5.077m 127.850ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.290s 421.931us 1 1 100.00
hmac_long_msg 36.520s 9.108ms 1 1 100.00
hmac_back_pressure 25.780s 1.332ms 1 1 100.00
hmac_datapath_stress 9.972m 26.416ms 1 1 100.00
hmac_wipe_secret 25.650s 683.244us 1 1 100.00
hmac_test_sha256_vectors 7.750s 189.275us 1 1 100.00
hmac_test_sha384_vectors 4.947m 13.992ms 1 1 100.00
hmac_test_sha512_vectors 18.840s 223.366us 1 1 100.00
hmac_test_hmac256_vectors 9.110s 310.729us 1 1 100.00
hmac_test_hmac384_vectors 5.440s 187.770us 1 1 100.00
hmac_test_hmac512_vectors 7.550s 671.761us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.290s 421.931us 1 1 100.00
hmac_long_msg 36.520s 9.108ms 1 1 100.00
hmac_back_pressure 25.780s 1.332ms 1 1 100.00
hmac_datapath_stress 9.972m 26.416ms 1 1 100.00
hmac_burst_wr 8.700s 449.287us 1 1 100.00
hmac_error 1.109m 1.587ms 1 1 100.00
hmac_wipe_secret 25.650s 683.244us 1 1 100.00
hmac_test_sha256_vectors 7.750s 189.275us 1 1 100.00
hmac_test_sha384_vectors 4.947m 13.992ms 1 1 100.00
hmac_test_sha512_vectors 18.840s 223.366us 1 1 100.00
hmac_test_hmac256_vectors 9.110s 310.729us 1 1 100.00
hmac_test_hmac384_vectors 5.440s 187.770us 1 1 100.00
hmac_test_hmac512_vectors 7.550s 671.761us 1 1 100.00
hmac_stress_all 5.077m 127.850ms 1 1 100.00
V2 stress_all hmac_stress_all 5.077m 127.850ms 1 1 100.00
V2 alert_test hmac_alert_test 0.570s 13.268us 1 1 100.00
V2 intr_test hmac_intr_test 0.690s 15.931us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.200s 157.064us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.200s 157.064us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.680s 36.537us 1 1 100.00
hmac_csr_rw 0.950s 73.487us 1 1 100.00
hmac_csr_aliasing 5.410s 1.198ms 1 1 100.00
hmac_same_csr_outstanding 0.890s 108.846us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.680s 36.537us 1 1 100.00
hmac_csr_rw 0.950s 73.487us 1 1 100.00
hmac_csr_aliasing 5.410s 1.198ms 1 1 100.00
hmac_same_csr_outstanding 0.890s 108.846us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.750s 265.062us 1 1 100.00
hmac_tl_intg_err 1.530s 106.566us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.530s 106.566us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.290s 421.931us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.960s 599.875us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.327m 5.250ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.860s 419.647us 1 1 100.00
TOTAL 28 28 100.00