I2C Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: `83a1436`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	56.820s	14.208ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.510s	2.898ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.610s	61.270us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.630s	53.162us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.080s	453.813us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.030s	203.094us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.700s	24.526us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.630s	53.162us	1	1	100.00
		i2c_csr_aliasing	1.030s	203.094us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.810s	242.582us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	26.537m	129.663ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	43.970s	8.497ms	1	1	100.00
V2	host_override	i2c_host_override	0.660s	19.226us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.011m	3.640ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.764m	2.688ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.750s	97.749us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.140s	2.089ms	1	1	100.00
		i2c_host_fifo_reset_rx	6.290s	178.922us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	50.740s	2.386ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.700s	2.230ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.640s	29.522us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.110s	3.049ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	41.500s	38.014ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.180s	1.657ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.980s	1.205ms	1	1	100.00
		i2c_target_intr_smoke	4.590s	2.299ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.190s	325.141us	1	1	100.00
		i2c_target_fifo_reset_tx	1.160s	369.122us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	14.450s	27.822ms	1	1	100.00
		i2c_target_stress_rd	14.980s	1.205ms	1	1	100.00
		i2c_target_intr_stress_wr	26.570s	20.283ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.070s	4.505ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	30.670s	3.107ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.580s	2.684ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.610s	10.106ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.200s	1.204ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.190s	653.830us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	43.970s	8.497ms	1	1	100.00
		i2c_host_perf_precise	21.350s	2.025ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.700s	2.230ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.690s	238.875us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.040s	1.958ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.070s	3.040ms	1	1	100.00
		i2c_target_nack_txstretch	1.360s	170.693us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	19.740s	685.435us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.390s	1.531ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.620s	16.875us	1	1	100.00
V2	intr_test	i2c_intr_test	0.660s	50.715us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.120s	1.564ms	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.120s	1.564ms	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.610s	61.270us	1	1	100.00
		i2c_csr_rw	0.630s	53.162us	1	1	100.00
		i2c_csr_aliasing	1.030s	203.094us	1	1	100.00
		i2c_same_csr_outstanding	1.090s	248.865us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.610s	61.270us	1	1	100.00
		i2c_csr_rw	0.630s	53.162us	1	1	100.00
		i2c_csr_aliasing	1.030s	203.094us	1	1	100.00
		i2c_same_csr_outstanding	1.090s	248.865us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.260s	313.223us	1	1	100.00
		i2c_sec_cm	1.050s	133.288us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.260s	313.223us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.420s	128.996us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.940s	32.132us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.030s	3.217ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 4 failures:

Test i2c_host_error_intr has 1 failures.

0.i2c_host_error_intr.32902076040713293062804439323801542891760007267013655589875147802707180182462
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 242581897 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 242581897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.65330143914543856222644590769228012871644550878972964601391414192258442779417
Line 175, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 129662746811 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 129662746811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_target_stress_all_with_rand_reset has 1 failures.
- 0.i2c_target_stress_all_with_rand_reset.93794125199541780216033463300220113591652511109442343755769204515891763457479
  Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3217352033 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 3217352033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.43301455113330157199069996351988809994521466056807223569261673930814875292721
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  29521508 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  29521508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test i2c_target_glitch has 1 failures.
  - 0.i2c_target_glitch.95600535314629508431219431375584965430152153408248024442565943201426854796792
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
```
  UVM_ERROR @ 3048570593 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 3048570593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.102404201110003634370393188252239882404585542631937049212210602951009846114115
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  32131652 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  32131652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.100006183341561784509219294128643010692016840980255120305704480552310144232386
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10106196950 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10106196950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.88001874919137291376475454757752686350720747227768537135786061547253271952567
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 128996354 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 128996354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```