KEYMGR Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.720s	40.083us	1	1	100.00
V1	random	keymgr_random	2.750s	80.229us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.000s	19.490us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.950s	24.285us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	8.880s	515.952us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.880s	132.262us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.720s	44.799us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.950s	24.285us	1	1	100.00
		keymgr_csr_aliasing	5.880s	132.262us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.230s	322.283us	1	1	100.00
V2	sideload	keymgr_sideload	2.310s	66.504us	1	1	100.00
		keymgr_sideload_kmac	2.790s	150.762us	1	1	100.00
		keymgr_sideload_aes	22.510s	1.880ms	1	1	100.00
		keymgr_sideload_otbn	2.810s	312.894us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.800s	134.687us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.480s	122.122us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.810s	106.895us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.100s	180.941us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	6.980s	555.231us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.300s	89.040us	1	1	100.00
V2	stress_all	keymgr_stress_all	1.740s	108.051us	0	1	0.00
V2	intr_test	keymgr_intr_test	0.780s	41.963us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.700s	46.587us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.790s	97.866us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.790s	97.866us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.000s	19.490us	1	1	100.00
		keymgr_csr_rw	0.950s	24.285us	1	1	100.00
		keymgr_csr_aliasing	5.880s	132.262us	1	1	100.00
		keymgr_same_csr_outstanding	1.280s	22.910us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.000s	19.490us	1	1	100.00
		keymgr_csr_rw	0.950s	24.285us	1	1	100.00
		keymgr_csr_aliasing	5.880s	132.262us	1	1	100.00
		keymgr_same_csr_outstanding	1.280s	22.910us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
		keymgr_tl_intg_err	3.070s	153.321us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.430s	577.837us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.430s	577.837us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.430s	577.837us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.430s	577.837us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	3.550s	388.051us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.070s	153.321us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.430s	577.837us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.230s	322.283us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.750s	80.229us	1	1	100.00
		keymgr_csr_rw	0.950s	24.285us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.750s	80.229us	1	1	100.00
		keymgr_csr_rw	0.950s	24.285us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.750s	80.229us	1	1	100.00
		keymgr_csr_rw	0.950s	24.285us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.480s	122.122us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	6.980s	555.231us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	6.980s	555.231us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.750s	80.229us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.360s	36.790us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	36.490s	10.777ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.480s	122.122us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	36.490s	10.777ms	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	36.490s	10.777ms	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	36.490s	10.777ms	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	8.010s	601.766us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	36.490s	10.777ms	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.260s	1.156ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
  • Test keymgr_stress_all has 1 failures.

    • 0.keymgr_stress_all.105757352897539433033640430179568382890799057795096035865123904409108300666933
      Line 247, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 108051030 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 108051030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---