KMAC/UNMASKED Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	18.950s	1.208ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.900s	28.529us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.430s	34.889us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.000s	663.438us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.260s	795.939us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.130s	70.603us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.430s	34.889us	1	1	100.00
		kmac_csr_aliasing	6.260s	795.939us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.900s	34.016us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.370s	70.187us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	7.658m	13.809ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.395m	64.719ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.160s	625.115us	1	1	100.00
		kmac_test_vectors_sha3_256	19.101m	33.929ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.470s	2.347ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.952m	114.578ms	1	1	100.00
		kmac_test_vectors_shake_128	24.705m	21.407ms	1	1	100.00
		kmac_test_vectors_shake_256	1.522m	59.352ms	1	1	100.00
		kmac_test_vectors_kmac	1.870s	416.909us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.920s	173.950us	1	1	100.00
V2	sideload	kmac_sideload	4.259m	26.103ms	1	1	100.00
V2	app	kmac_app	3.301m	27.901ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.822m	46.727ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.629m	26.297ms	1	1	100.00
V2	error	kmac_error	1.280m	18.752ms	1	1	100.00
V2	key_error	kmac_key_error	7.160s	4.455ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.383m	10.045ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.440s	916.822us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.200s	2.785ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	32.960s	6.004ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.170s	60.300us	1	1	100.00
V2	stress_all	kmac_stress_all	13.991m	149.760ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.860s	19.266us	1	1	100.00
V2	alert_test	kmac_alert_test	0.910s	30.723us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.230s	116.853us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.230s	116.853us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.900s	28.529us	1	1	100.00
		kmac_csr_rw	1.430s	34.889us	1	1	100.00
		kmac_csr_aliasing	6.260s	795.939us	1	1	100.00
		kmac_same_csr_outstanding	2.280s	440.789us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.900s	28.529us	1	1	100.00
		kmac_csr_rw	1.430s	34.889us	1	1	100.00
		kmac_csr_aliasing	6.260s	795.939us	1	1	100.00
		kmac_same_csr_outstanding	2.280s	440.789us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.220s	49.055us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.220s	49.055us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.220s	49.055us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.220s	49.055us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.040s	194.962us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	33.890s	3.344ms	1	1	100.00
		kmac_tl_intg_err	3.740s	244.023us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.740s	244.023us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.170s	60.300us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	18.950s	1.208ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.259m	26.103ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.220s	49.055us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	33.890s	3.344ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	33.890s	3.344ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	33.890s	3.344ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	18.950s	1.208ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.170s	60.300us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	33.890s	3.344ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.026m	1.347ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	18.950s	1.208ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.030m	58.087ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.93658551702408111445448510121743416436853363408312196781459265985321267022333
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10045379383 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xeea9000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10045379383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.39484392567216763787861121548747921997482666713341168385545491473372761271914
      Line 340, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58087071352 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 58087071352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---