OTBN Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 13.000s 43.963us 0 1 0.00
V1 single_binary otbn_single 9.000s 33.704us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 13.387us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 16.895us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 9.000s 553.433us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 5.000s 17.178us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 62.684us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 16.895us 1 1 100.00
otbn_csr_aliasing 5.000s 17.178us 1 1 100.00
V1 mem_walk otbn_mem_walk 14.000s 3.474ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 11.000s 227.168us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 22.000s 107.128us 0 1 0.00
V2 multi_error otbn_multi_err 2.167m 653.757us 0 1 0.00
V2 back_to_back otbn_multi 50.000s 1.540ms 0 1 0.00
V2 stress_all otbn_stress_all 23.000s 260.061us 0 1 0.00
V2 lc_escalation otbn_escalate 12.000s 83.837us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 23.048us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 8.000s 18.971us 0 1 0.00
V2 alert_test otbn_alert_test 5.000s 71.093us 1 1 100.00
V2 intr_test otbn_intr_test 5.000s 17.246us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 8.000s 228.795us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 8.000s 228.795us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 13.387us 1 1 100.00
otbn_csr_rw 4.000s 16.895us 1 1 100.00
otbn_csr_aliasing 5.000s 17.178us 1 1 100.00
otbn_same_csr_outstanding 4.000s 31.355us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 13.387us 1 1 100.00
otbn_csr_rw 4.000s 16.895us 1 1 100.00
otbn_csr_aliasing 5.000s 17.178us 1 1 100.00
otbn_same_csr_outstanding 4.000s 31.355us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 9.000s 35.422us 0 1 0.00
otbn_dmem_err 8.000s 44.315us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 5.000s 11.897us 0 1 0.00
otbn_controller_ispr_rdata_err 11.000s 57.417us 0 1 0.00
otbn_mac_bignum_acc_err 8.000s 53.659us 0 1 0.00
otbn_urnd_err 7.000s 43.655us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 27.580us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 12.502us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 6.000s 22.728us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 1.383m 1.983ms 1 1 100.00
otbn_tl_intg_err 10.000s 124.717us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 20.000s 218.322us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 13.000s 43.963us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 8.000s 44.315us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 9.000s 35.422us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 10.000s 124.717us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 12.000s 83.837us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 9.000s 35.422us 0 1 0.00
otbn_dmem_err 8.000s 44.315us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 23.048us 1 1 100.00
otbn_illegal_mem_acc 5.000s 27.580us 1 1 100.00
otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 9.000s 35.422us 0 1 0.00
otbn_dmem_err 8.000s 44.315us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 23.048us 1 1 100.00
otbn_illegal_mem_acc 5.000s 27.580us 1 1 100.00
otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 12.000s 83.837us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 9.000s 35.422us 0 1 0.00
otbn_dmem_err 8.000s 44.315us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 23.048us 1 1 100.00
otbn_illegal_mem_acc 5.000s 27.580us 1 1 100.00
otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 27.712us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 100.896us 0 1 0.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.700m 349.364us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.700m 349.364us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 7.000s 28.417us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 6.000s 100.811us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 36.563us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 36.563us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 5.000s 10.193us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 50.000s 1.540ms 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 18.000s 382.480us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 9.000s 33.704us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 1.383m 1.983ms 1 1 100.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 3.167m 3.135ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets