83a1436| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 3.000s | 22.939us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 31.604us | 1 | 1 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 15.434us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 3.000s | 516.475us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 80.655us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 3.000s | 24.580us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 15.434us | 1 | 1 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 80.655us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | perf | pattgen_perf | 24.650m | 600.000ms | 0 | 1 | 0.00 |
| V2 | cnt_rollover | cnt_rollover | 3.000s | 76.558us | 1 | 1 | 100.00 |
| V2 | error | pattgen_error | 2.000s | 101.953us | 1 | 1 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.385h | 8.536s | 0 | 1 | 0.00 |
| V2 | alert_test | pattgen_alert_test | 2.000s | 14.074us | 1 | 1 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 3.000s | 17.417us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 4.000s | 42.606us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 4.000s | 42.606us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 31.604us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 2.000s | 15.434us | 1 | 1 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 80.655us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 35.107us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 31.604us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 2.000s | 15.434us | 1 | 1 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 80.655us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 35.107us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 6 | 8 | 75.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 291.240us | 1 | 1 | 100.00 |
| pattgen_sec_cm | 2.000s | 151.714us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 291.240us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 50.000s | 11.112ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 2.000m | 10.041ms | 0 | 1 | 0.00 | |
| TOTAL | 14 | 18 | 77.78 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.pattgen_perf.66392764136602926530417450183780699618770133884038742084934836757838301631607
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
0.pattgen_inactive_level.63658015477093208364377689902933131335859728120073012268373648461797160370494
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10040629864 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x439f0710, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10040629864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.pattgen_stress_all_with_rand_reset.46065160381545948268756450886459184428359866420646565206835562362260959377398
Line 119, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3968355727 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3968393080 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3968393080 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3968498344 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
0.pattgen_stress_all.2927674485615347013794913975625991035776944679858594214938037575422918460228
Line 130, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 8536367433977 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
-----------------------------------------
Name Type Size Value
-----------------------------------------
exp_item pattgen_item - @463270