RV_TIMER Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.610s	40.522us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.680s	35.055us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.560s	14.068us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.820s	729.245us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.700s	78.566us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.140s	27.352us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.560s	14.068us	1	1	100.00
		rv_timer_csr_aliasing	0.700s	78.566us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.780s	354.540us	1	1	100.00
V2	disabled	rv_timer_disabled	1.300s	748.036us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.605m	146.602ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.605m	146.602ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.400s	18.027ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.630s	14.308us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.570s	42.593us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.250s	52.885us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.250s	52.885us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.680s	35.055us	1	1	100.00
		rv_timer_csr_rw	0.560s	14.068us	1	1	100.00
		rv_timer_csr_aliasing	0.700s	78.566us	1	1	100.00
		rv_timer_same_csr_outstanding	0.760s	67.170us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.680s	35.055us	1	1	100.00
		rv_timer_csr_rw	0.560s	14.068us	1	1	100.00
		rv_timer_csr_aliasing	0.700s	78.566us	1	1	100.00
		rv_timer_same_csr_outstanding	0.760s	67.170us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	0.990s	233.958us	1	1	100.00
		rv_timer_tl_intg_err	1.210s	77.786us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.210s	77.786us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.720s	62.355us	1	1	100.00
V3	max_value	rv_timer_max	0.650s	16.089us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	44.150s	5.211ms	1	1	100.00
V3		TOTAL			3	3	100.00
		TOTAL			19	19	100.00