SPI_DEVICE/1R1W Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.090m	34.139ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.050s	37.493us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.760s	312.624us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.920s	3.771ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.900s	1.298ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.740s	106.294us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.760s	312.624us	1	1	100.00
		spi_device_csr_aliasing	14.900s	1.298ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.800s	96.146us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.660s	233.578us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.890s	39.046us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	17.091us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	3.457us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.100s	508.959us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.100s	508.959us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.340s	3.789ms	1	1	100.00
		spi_device_tpm_sts_read	0.890s	327.480us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	22.490s	6.438ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	11.910s	26.789ms	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.030s	1.349ms	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.030s	1.349ms	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.770s	417.878us	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.770s	417.878us	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.770s	417.878us	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.770s	417.878us	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.770s	417.878us	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.460s	14.929ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	45.880s	14.348ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	45.880s	14.348ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	45.880s	14.348ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.860s	36.781us	1	1	100.00
		spi_device_read_buffer_direct	2.760s	156.143us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	45.880s	14.348ms	1	1	100.00
		spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	9.490s	2.264ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.560s	189.715us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.560s	189.715us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.090m	34.139ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.161m	135.679ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.160s	41.429us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.740s	21.533us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.650s	15.660us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.720s	102.390us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.720s	102.390us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.050s	37.493us	1	1	100.00
		spi_device_csr_rw	1.760s	312.624us	1	1	100.00
		spi_device_csr_aliasing	14.900s	1.298ms	1	1	100.00
		spi_device_same_csr_outstanding	2.210s	240.118us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.050s	37.493us	1	1	100.00
		spi_device_csr_rw	1.760s	312.624us	1	1	100.00
		spi_device_csr_aliasing	14.900s	1.298ms	1	1	100.00
		spi_device_same_csr_outstanding	2.210s	240.118us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.050s	50.712us	1	1	100.00
		spi_device_tl_intg_err	15.410s	5.935ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.410s	5.935ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	25.600s	8.300ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.21789732016501957586532424065756603318479438124776139116986194619538607478657
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  11182037 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[90])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  11182037 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  11182037 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[986])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.58972990202625807893351592494558486464963066199397567064446098726398712383402
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1071310 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x87865d [100001111000011001011101] vs 0x0 [0])
        UVM_ERROR @   1087310 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbd4583 [101111010100010110000011] vs 0x0 [0])
        UVM_ERROR @   1175310 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4613e6 [10001100001001111100110] vs 0x0 [0])
        UVM_ERROR @   1209310 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x345ea5 [1101000101111010100101] vs 0x0 [0])
        UVM_ERROR @   1229310 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x170d0e [101110000110100001110] vs 0x0 [0])