SPI_DEVICE/2P Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 3.051m 125.435ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.290s 38.344us 1 1 100.00
V1 csr_rw spi_device_csr_rw 1.440s 178.913us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 16.530s 6.502ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 16.500s 927.865us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.420s 64.064us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.440s 178.913us 1 1 100.00
spi_device_csr_aliasing 16.500s 927.865us 1 1 100.00
V1 mem_walk spi_device_mem_walk 0.740s 29.583us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.150s 55.416us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 0.810s 19.615us 1 1 100.00
V2 mem_parity spi_device_mem_parity 0.890s 27.597us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 0.670s 20.475us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 0.890s 14.615us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 0.890s 14.615us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 5.090s 7.567ms 1 1 100.00
spi_device_tpm_sts_read 0.750s 116.537us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 23.170s 5.904ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 8.780s 6.467ms 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 3.980s 658.526us 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 3.980s 658.526us 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 2.020s 85.145us 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 2.020s 85.145us 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 2.020s 85.145us 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 2.020s 85.145us 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 2.020s 85.145us 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 3.700s 1.671ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 11.400s 4.025ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 11.400s 4.025ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 11.400s 4.025ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 55.240s 6.075ms 1 1 100.00
spi_device_read_buffer_direct 9.760s 1.513ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 11.400s 4.025ms 1 1 100.00
spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 quad_spi spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 dual_spi spi_device_flash_all 1.143m 34.412ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 2.250s 67.525us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 2.250s 67.525us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 3.051m 125.435ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 2.200m 31.052ms 1 1 100.00
V2 stress_all spi_device_stress_all 7.058m 69.052ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.000s 44.247us 1 1 100.00
V2 intr_test spi_device_intr_test 0.960s 34.545us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.300s 125.566us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.300s 125.566us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.290s 38.344us 1 1 100.00
spi_device_csr_rw 1.440s 178.913us 1 1 100.00
spi_device_csr_aliasing 16.500s 927.865us 1 1 100.00
spi_device_same_csr_outstanding 2.850s 57.468us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.290s 38.344us 1 1 100.00
spi_device_csr_rw 1.440s 178.913us 1 1 100.00
spi_device_csr_aliasing 16.500s 927.865us 1 1 100.00
spi_device_same_csr_outstanding 2.850s 57.468us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.180s 91.613us 1 1 100.00
spi_device_tl_intg_err 6.870s 391.416us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 6.870s 391.416us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 0.960s 108.850us 1 1 100.00
TOTAL 33 33 100.00