SPI_HOST Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	15.000s	1.049ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	7.000s	53.024us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	6.000s	17.871us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	60.705us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	20.804us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	129.000us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	6.000s	17.871us	1	1	100.00
		spi_host_csr_aliasing	3.000s	20.804us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	7.000s	46.182us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	7.000s	69.970us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	51.519us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	117.834us	1	1	100.00
		spi_host_error_cmd	2.000s	23.358us	1	1	100.00
		spi_host_event	23.000s	2.924ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	76.185us	1	1	100.00
V2	speed	spi_host_speed	2.000s	76.185us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	76.185us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	83.623us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	42.880us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	76.185us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	76.185us	1	1	100.00
V2	duplex	spi_host_smoke	15.000s	1.049ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	15.000s	1.049ms	1	1	100.00
V2	stress_all	spi_host_stress_all	43.000s	1.327ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	671.943us	1	1	100.00
V2	stall	spi_host_status_stall	22.000s	2.610ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	7.000s	258.082us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	117.834us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	18.628us	1	1	100.00
V2	intr_test	spi_host_intr_test	7.000s	20.318us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	10.000s	99.256us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	10.000s	99.256us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	7.000s	53.024us	1	1	100.00
		spi_host_csr_rw	6.000s	17.871us	1	1	100.00
		spi_host_csr_aliasing	3.000s	20.804us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	27.418us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	7.000s	53.024us	1	1	100.00
		spi_host_csr_rw	6.000s	17.871us	1	1	100.00
		spi_host_csr_aliasing	3.000s	20.804us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	27.418us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	8.000s	1.107ms	1	1	100.00
		spi_host_sec_cm	3.000s	40.709us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	8.000s	1.107ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.867m	54.982ms	1	1	100.00
		TOTAL			26	26	100.00