SRAM_CTRL/MAIN Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	47.560s	1.493ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.900s	22.732us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.980s	19.446us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.490s	44.771us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.910s	19.226us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.540s	1.549ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.980s	19.446us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	19.226us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.638m	14.869ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.822m	10.234ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.610m	44.306ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.574m	3.570ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.648m	607.052ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.179m	123.704ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	19.270s	17.588ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.079m	58.087ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.930s	939.626us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.438m	13.495ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	31.930s	1.951ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	21.040s	1.447ms	1	1	100.00
		sram_ctrl_throughput_w_readback	12.380s	1.445ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.048m	3.488ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.060s	692.998us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	53.966m	104.102ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.880s	14.809us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.980s	234.406us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.980s	234.406us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.900s	22.732us	1	1	100.00
		sram_ctrl_csr_rw	0.980s	19.446us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	19.226us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	55.931us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.900s	22.732us	1	1	100.00
		sram_ctrl_csr_rw	0.980s	19.446us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	19.226us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	55.931us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	39.300s	29.364ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.860s	3.071us	0	1	0.00
		sram_ctrl_tl_intg_err	3.180s	979.479us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.860s	3.071us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.180s	979.479us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.048m	3.488ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.048m	3.488ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.980s	19.446us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.079m	58.087ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.079m	58.087ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.079m	58.087ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	19.270s	17.588ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.410s	1.408ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	39.300s	29.364ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.260s	698.392us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	47.560s	1.493ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	47.560s	1.493ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.079m	58.087ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.860s	3.071us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	19.270s	17.588ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.860s	3.071us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.860s	3.071us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	47.560s	1.493ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.860s	3.071us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.740s	9.622ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.92069560364094955984016041565016323027777944177928210731034874950869725252876
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3071156 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3071156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---