SRAM_CTRL/RET Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.440s	46.104us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.840s	32.401us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.850s	25.611us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.730s	177.973us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.820s	81.182us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.110s	32.341us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.850s	25.611us	1	1	100.00
		sram_ctrl_csr_aliasing	0.820s	81.182us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.820s	1.766ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.420s	161.746us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.103m	2.593ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.756m	2.306ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	47.530s	8.805ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.779m	4.623ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.200s	3.065ms	1	1	100.00
V2	executable	sram_ctrl_executable	40.170s	282.072us	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.410s	614.895us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.440m	7.447ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.620s	207.253us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	50.790s	285.789us	1	1	100.00
		sram_ctrl_throughput_w_readback	49.280s	1.101ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.335m	86.913ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.000s	227.857us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	21.649m	46.602ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.680s	18.470us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.620s	182.682us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.620s	182.682us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.840s	32.401us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	25.611us	1	1	100.00
		sram_ctrl_csr_aliasing	0.820s	81.182us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.020s	31.712us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.840s	32.401us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	25.611us	1	1	100.00
		sram_ctrl_csr_aliasing	0.820s	81.182us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.020s	31.712us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.570s	430.076us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.650s	7.140us	0	1	0.00
		sram_ctrl_tl_intg_err	2.010s	787.525us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.650s	7.140us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.010s	787.525us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.335m	86.913ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.335m	86.913ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.850s	25.611us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.170s	282.072us	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.170s	282.072us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.170s	282.072us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.200s	3.065ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.270s	84.602us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.570s	430.076us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.310s	120.157us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.440s	46.104us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.440s	46.104us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.170s	282.072us	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.650s	7.140us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.200s	3.065ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.650s	7.140us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.650s	7.140us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.440s	46.104us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.650s	7.140us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.195m	10.013ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.109158830189564191995656291535940614893443330613479441527942778328868581573672
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        UVM_ERROR @   7139755 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7139755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---