SYSRST_CTRL Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.640s	2.111ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.770s	2.466ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	1.650s	2.218ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.540s	2.261ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.080s	6.012ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	4.320s	2.040ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	5.480s	4.077ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.850s	2.951ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.620s	2.049ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	4.320s	2.040ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.850s	2.951ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	1.867m	59.801ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	50.280s	83.470ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	6.150s	3.679ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	1.380s	3.416ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	1.740s	2.529ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	4.620s	2.126ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	5.540s	2.765ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.070s	2.665ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.670s	5.282ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	11.620s	35.849ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	37.910s	79.286ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	4.070s	2.013ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.350s	2.028ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.540s	2.029ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.540s	2.029ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.080s	6.012ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.320s	2.040ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.850s	2.951ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	3.630s	5.286ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.080s	6.012ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.320s	2.040ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.850s	2.951ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	3.630s	5.286ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	39.040s	22.011ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	40.850s	22.210ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	40.850s	22.210ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	8.300s	4.250ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.42391944314892509264810453765706491678871100271576293810890253012052075868606
      Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 2207722990 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
        UVM_INFO @ 2320222990 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
        UVM_INFO @ 5260222990 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
        UVM_INFO @ 5281967991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---