UART Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.100s	249.089us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.730s	13.161us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.680s	11.407us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.960s	447.879us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	123.581us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.870s	41.726us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.680s	11.407us	1	1	100.00
		uart_csr_aliasing	0.760s	123.581us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	28.670s	35.836ms	1	1	100.00
V2	parity	uart_smoke	1.100s	249.089us	1	1	100.00
		uart_tx_rx	28.670s	35.836ms	1	1	100.00
V2	parity_error	uart_intr	1.600m	92.179ms	1	1	100.00
		uart_rx_parity_err	1.323m	67.801ms	1	1	100.00
V2	watermark	uart_tx_rx	28.670s	35.836ms	1	1	100.00
		uart_intr	1.600m	92.179ms	1	1	100.00
V2	fifo_full	uart_fifo_full	32.210s	28.920ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	18.500s	27.453ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.129m	101.269ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.600m	92.179ms	1	1	100.00
V2	rx_break_err	uart_intr	1.600m	92.179ms	1	1	100.00
V2	rx_timeout	uart_intr	1.600m	92.179ms	1	1	100.00
V2	perf	uart_perf	13.726m	24.438ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.080s	4.775ms	1	1	100.00
V2	line_loopback	uart_loopback	2.080s	4.775ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	38.340s	102.567ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.580s	2.912ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.950s	1.182ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.110s	4.541ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.078m	220.844ms	1	1	100.00
V2	stress_all	uart_stress_all	1.163m	135.345ms	1	1	100.00
V2	alert_test	uart_alert_test	0.780s	122.529us	1	1	100.00
V2	intr_test	uart_intr_test	0.530s	65.789us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.260s	103.964us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.260s	103.964us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.730s	13.161us	1	1	100.00
		uart_csr_rw	0.680s	11.407us	1	1	100.00
		uart_csr_aliasing	0.760s	123.581us	1	1	100.00
		uart_same_csr_outstanding	0.730s	59.952us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.730s	13.161us	1	1	100.00
		uart_csr_rw	0.680s	11.407us	1	1	100.00
		uart_csr_aliasing	0.760s	123.581us	1	1	100.00
		uart_same_csr_outstanding	0.730s	59.952us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.360s	367.973us	1	1	100.00
		uart_tl_intg_err	1.110s	202.835us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.110s	202.835us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	11.120s	5.819ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00