CHIP Simulation Results

Monday September 08 2025 17:16:17 UTC

GitHub Revision: `83a1436`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.818m	2.859ms	1	1	100.00
		chip_sw_example_rom	1.463m	2.811ms	1	1	100.00
		chip_sw_example_manufacturer	2.030m	3.208ms	1	1	100.00
		chip_sw_example_concurrency	2.032m	3.085ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.264m	5.728ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.416m	6.019ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.555m	8.374ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.444h	39.417ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.974m	5.808ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.444h	39.417ms	1	1	100.00
		chip_csr_rw	6.416m	6.019ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.760s	193.792us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.045m	4.517ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.045m	4.517ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.045m	4.517ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.850m	4.892ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.850m	4.892ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.906m	3.923ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.042m	4.147ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.265m	3.900ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	17.321m	8.856ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	30.803m	13.359ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.795m	7.794ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.010m	5.396ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.010m	5.396ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.576m	2.458ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.663m	3.152ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.308m	4.367ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	16.736m	14.825ms	1	1	100.00
		chip_tap_straps_testunlock0	1.958m	2.903ms	1	1	100.00
		chip_tap_straps_rma	3.673m	4.217ms	1	1	100.00
		chip_tap_straps_prod	16.415m	14.048ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.295m	3.238ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.114m	9.138ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.952m	6.032ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.952m	6.032ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.940m	7.586ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	24.614m	15.818ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.423m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.169m	5.525ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.079m	19.103ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.009m	2.638ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.570m	6.920ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.048m	3.510ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.255m	7.651ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.940m	3.460ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.123m	5.456ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.679m	2.993ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.304m	3.371ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.210m	6.996ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.994m	5.482ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.198m	3.156ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.994m	5.482ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.033m	2.527ms	1	1	100.00
		chip_sw_aes_smoketest	3.418m	3.042ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.641m	3.332ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.272m	2.225ms	1	1	100.00
		chip_sw_csrng_smoketest	1.956m	3.065ms	1	1	100.00
		chip_sw_entropy_src_smoketest	12.625m	5.750ms	1	1	100.00
		chip_sw_gpio_smoketest	2.487m	2.506ms	1	1	100.00
		chip_sw_hmac_smoketest	3.067m	2.682ms	1	1	100.00
		chip_sw_kmac_smoketest	3.168m	3.013ms	1	1	100.00
		chip_sw_otbn_smoketest	17.696m	8.726ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.022m	5.687ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	5.491m	5.629ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.585m	2.423ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.464m	2.632ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.477m	2.475ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.253m	2.494ms	1	1	100.00
		chip_sw_uart_smoketest	1.996m	3.214ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.801m	2.672ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.481m	5.666ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.150h	61.352ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.801m	15.332ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.279m	4.585ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.399m	2.782ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.421m	3.339ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.997h	54.628ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.997h	55.908ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	48.840s	2.195ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	48.840s	2.195ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.444h	39.417ms	1	1	100.00
		chip_same_csr_outstanding	39.195m	28.901ms	1	1	100.00
		chip_csr_hw_reset	3.264m	5.728ms	1	1	100.00
		chip_csr_rw	6.416m	6.019ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.444h	39.417ms	1	1	100.00
		chip_same_csr_outstanding	39.195m	28.901ms	1	1	100.00
		chip_csr_hw_reset	3.264m	5.728ms	1	1	100.00
		chip_csr_rw	6.416m	6.019ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	21.480s	334.802us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.240s	50.455us	1	1	100.00
		xbar_smoke_large_delays	54.900s	8.434ms	1	1	100.00
		xbar_smoke_slow_rsp	35.580s	4.011ms	1	1	100.00
		xbar_random_zero_delays	26.800s	443.431us	1	1	100.00
		xbar_random_large_delays	2.360m	23.110ms	1	1	100.00
		xbar_random_slow_rsp	1.458m	9.641ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	33.850s	1.314ms	1	1	100.00
		xbar_error_and_unmapped_addr	25.810s	984.525us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	48.290s	2.216ms	1	1	100.00
		xbar_error_and_unmapped_addr	25.810s	984.525us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.166m	2.677ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.447m	54.475ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	13.790s	261.099us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.473m	2.789ms	1	1	100.00
		xbar_stress_all_with_error	1.681m	4.545ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.000m	346.343us	1	1	100.00
		xbar_stress_all_with_reset_error	4.460m	3.154ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.801m	15.332ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.981m	30.109ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.300m	15.087ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.232m	12.259ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.224m	15.757ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.830m	15.558ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.368m	15.929ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.135m	15.706ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.350s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.740s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	22.480s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.310s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.710s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.130s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	21.730s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.940s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	20.220s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.350s	10.100us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.980s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.400s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.570s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.930s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.880s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.340s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.690s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.920s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.210s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	21.070s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.400s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.470s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.370s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.560s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.490s	10.100us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.562m	10.967ms	1	1	100.00
		rom_e2e_asm_init_dev	40.703m	15.595ms	1	1	100.00
		rom_e2e_asm_init_prod	41.913m	15.393ms	1	1	100.00
		rom_e2e_asm_init_prod_end	42.347m	16.522ms	1	1	100.00
		rom_e2e_asm_init_rma	40.087m	15.533ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.179m	15.576ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	39.036m	15.100ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.272m	15.535ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.591m	16.361ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	51.460m	34.495ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	51.460m	34.495ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.234m	3.224ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.009m	2.638ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.570m	3.068ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.022m	2.824ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	28.840m	12.441ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.431m	2.852ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.244m	4.740ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.332m	6.130ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	10.067m	5.441ms	1	1	100.00
		chip_plic_all_irqs_10	5.065m	3.707ms	1	1	100.00
		chip_plic_all_irqs_20	5.905m	3.815ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	4.161m	4.033ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.455m	11.657ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.895m	3.417ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.536m	2.476ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	7.972m	9.605ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.459m	7.363ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.948m	6.987ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.395m	7.973ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.391h	255.508ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.361m	3.997ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.022m	5.687ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.361m	3.997ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.481m	7.928ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.481m	7.928ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.438m	6.647ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.397m	4.580ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.967m	5.965ms	1	1	100.00
		chip_sw_aes_idle	3.022m	2.824ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.150m	3.260ms	1	1	100.00
		chip_sw_kmac_idle	2.105m	2.947ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.311m	3.645ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.387m	4.935ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.524m	4.546ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.454m	4.548ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.989m	9.159ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.853m	4.104ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.737m	4.744ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.710m	4.585ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.483m	4.896ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.381m	3.408ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.472m	5.127ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.940m	7.586ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.444m	7.464ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.710m	4.585ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.483m	4.896ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.423m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.169m	5.525ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.079m	19.103ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.009m	2.638ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.570m	6.920ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.048m	3.510ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.255m	7.651ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.940m	3.460ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.123m	5.456ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.679m	2.993ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.422m	2.704ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.266m	4.856ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.853m	7.183ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.017m	24.919ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.517m	2.718ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.256m	3.362ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	21.678m	12.472ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.296m	2.755ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	6.477m	5.248ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.983m	17.702ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	35.179m	17.709ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.940m	7.586ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.779m	4.485ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.219m	3.608ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.332m	6.130ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.459m	7.363ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.029m	7.533ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.374m	4.184ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.329m	6.291ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.246m	2.974ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.206h	25.982ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.446m	3.443ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.971m	6.838ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.446m	3.443ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.029m	7.533ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.107m	2.561ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.503m	21.246ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.210m	5.395ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.169m	5.525ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.466m	4.159ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.423m	4.106ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	52.048m	44.128ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.503m	21.246ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.055m	2.835ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	25.784m	12.213ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.768m	3.759ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	52.048m	44.128ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.768m	3.759ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.768m	3.759ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.768m	3.759ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.768m	3.759ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.332m	6.130ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.104m	5.883ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.798m	5.363ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.713m	5.161ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.713m	5.161ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.885m	3.007ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.048m	3.510ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.150m	3.260ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.893m	2.443ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.446m	3.927ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.831m	4.516ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.260m	5.115ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.226m	4.783ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.214m	4.587ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	25.784m	12.213ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.255m	7.651ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.659m	8.247ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	28.840m	12.441ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	41.607m	14.402ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.675m	3.174ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.692m	3.071ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.940m	3.460ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	25.784m	12.213ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.499m	2.249ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	24.693m	10.129ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.105m	2.947ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.244m	4.740ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	16.736m	14.825ms	1	1	100.00
		chip_tap_straps_rma	3.673m	4.217ms	1	1	100.00
		chip_tap_straps_prod	16.415m	14.048ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.055m	3.595ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	12.437m	7.241ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.768m	3.759ms	1	1	100.00
		chip_sw_flash_rma_unlocked	52.048m	44.128ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.942m	4.048ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.342m	6.652ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.363m	7.469ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.101m	7.308ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.784m	12.213ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.747m	9.201ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.368m	6.509ms	1	1	100.00
		chip_prim_tl_access	2.104m	5.883ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.444m	7.464ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.853m	4.104ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.737m	4.744ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.710m	4.585ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.483m	4.896ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.381m	3.408ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.472m	5.127ms	1	1	100.00
		chip_tap_straps_dev	16.736m	14.825ms	1	1	100.00
		chip_tap_straps_rma	3.673m	4.217ms	1	1	100.00
		chip_tap_straps_prod	16.415m	14.048ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.085m	11.301ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.066m	3.224ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.836m	3.565ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.431m	3.697ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.935m	3.687ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.292m	31.845ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.085m	11.301ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.065h	46.881ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.087h	47.365ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.202m	8.570ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.063h	48.215ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.292m	31.845ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	59.100s	2.060ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.161m	2.910ms	1	1	100.00
		rom_volatile_raw_unlock	1.025m	2.221ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.017m	16.460ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.079m	19.103ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.967m	5.965ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.967m	5.965ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.967m	5.965ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.659m	3.238ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.503m	21.246ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.659m	3.238ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.784m	12.213ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.522m	5.037ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.621m	2.323ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.503m	21.246ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.659m	3.238ms	1	1	100.00
		chip_sw_keymgr_key_derivation	25.784m	12.213ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.522m	5.037ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.621m	2.323ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.876m	4.138ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.055m	3.595ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.942m	4.048ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.342m	6.652ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.363m	7.469ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	10.101m	7.308ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.907m	10.071ms	1	1	100.00
		chip_prim_tl_access	2.104m	5.883ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.104m	5.883ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.845m	9.690ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.454m	8.785ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.303m	23.172ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.295m	7.208ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.268m	6.912ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.589m	5.925ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	11.613m	21.270ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.905m	14.409ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.481m	7.928ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	15.967m	13.762ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.480m	4.773ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.454m	8.785ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.815m	3.485ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	39.469m	44.522ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.943m	7.242ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.983m	6.878ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.445m	24.860ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.363m	8.231ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	17.037m	11.207ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	26.854m	29.038ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.140m	2.991ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.332m	6.130ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.747m	9.201ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.747m	9.201ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.037m	11.207ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	27.445m	24.860ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.480m	4.773ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.022m	5.687ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.678m	3.648ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.587m	3.568ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.009m	4.674ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.455m	11.657ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.355m	2.627ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.332m	6.130ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.948m	6.987ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.405m	4.808ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.317m	4.879ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.629m	2.645ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.621m	2.323ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.587m	3.568ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.587m	3.568ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	13.254m	12.751ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.234m	13.189ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.678m	3.648ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.791m	4.270ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.454m	5.770ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.673m	4.217ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.085m	11.301ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	10.067m	5.441ms	1	1	100.00
		chip_plic_all_irqs_10	5.065m	3.707ms	1	1	100.00
		chip_plic_all_irqs_20	5.905m	3.815ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.363m	2.659ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.874m	2.981ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.801m	15.332ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.032m	5.816ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.303m	2.937ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.536m	3.441ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.161m	2.731ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.522m	5.037ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.123m	5.456ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.804m	9.108ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.483m	7.052ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.368m	6.509ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.332m	6.130ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.952m	6.032ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.363m	8.231ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.576m	23.478ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.591m	2.904ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	4.019m	4.002ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.863m	4.449ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.576m	23.478ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.576m	23.478ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.416m	20.760ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.416m	20.760ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.018m	6.330ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	51.460m	34.495ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.635m	3.017ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.845m	2.718ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.453m	3.952ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.954m	4.250ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.579m	8.310ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.441h	31.176ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.331m	12.468ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.508m	2.765ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.076m	3.438ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.300m	2.572ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.629h	72.416ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.901m	3.297ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	9.613m	13.847ms	0	1	0.00
		rom_e2e_jtag_debug_dev	3.091m	3.874ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.674m	12.802ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.658m	4.784ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.076m	4.298ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.185m	4.652ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.265s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.970m	5.010ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.047m	2.439ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	13.778m	5.627ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	27.008m	11.009ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.440m	2.088ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.886m	5.244ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	59.860s	2.552ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.344m	4.518ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.853m	5.488ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.793m	5.047ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.037m	11.207ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	9.613m	13.847ms	0	1	0.00
		rom_e2e_jtag_debug_dev	3.091m	3.874ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.674m	12.802ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.532m	4.346ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.332m	6.130ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.548h	38.563ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.548h	38.563ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.707m	3.397ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.850m	4.892ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	53.035m	19.363ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.973m	3.098ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.908m	4.912ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.791m	2.838ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.977m	3.475ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.420m	3.573ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	16.881s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.462m	3.595ms	1	1	100.00
		TOTAL			282	325	86.77

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.73137819851346946644741005163706776166126918750770202126189644147670280923158
    Line 466, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.73702822559997798669238610544991828837827850916027960621479291958408948964358
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.10403563713904744023639164623714956686154140460593290449755727475432241679811
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.87999359756666224295073769732848955528841876276302858557108666380064218567402
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4954521718256884131411693718905148925059832032701156167841708038385140735215
    Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.89478973715229675435470226220395764154914521040570957840175104662535276516361
    Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.25633213653458656150639542012048141174836422046695431343166049630159826938604
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.53547170907812938378088679845216809990889470638529868846874484434261727753850
    Line 467, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.12682205708437198859225612232528890757570953849416598983230924864407268399137
    Line 480, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.24840592647162671931303811814667253724247788164758696554443809684603216786779
    Line 487, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.17802662446957425213575319052691170871698698577290392893224615051227523662275
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.66041671228539694462205128143689980723480458393220008004342841344437414345278
    Line 530, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.78165503594423375822432813437624183323762393647587568696980791478488703696087
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.99569077353620841271581947736027397770314271040165070633426402987665425990071
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.162s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.73505845807998143188817526140431328942769421220051918995221517243231877704599
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.135s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.26636465176236079044907386302432080560923539115611994548578030108908963786547
    Line 545, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.57757618342394538168255502100293513721229577625332855275262380065383803878854
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.9252036079144731768474645888794596619085228041149943102881809295924851059009
    Line 606, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.113947487790437333392472780203542190372102094964271174503251576009647120771690
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.37441157627240747181661860757890130549351370343356915128869378323095727551636
    Line 628, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2458.411000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2458.411000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.109015938608951779726668042477325984430507263301045109711077058862128452669072
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2937.221785 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2937.221785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@99555) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.31353517206226311194081911881417420491295343484672466789175494486076967422550
Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3567.842474 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@99555) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3567.842474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.93233958179799430089415322745626789192468025598025386206706965927090363808916
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34494.782919 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34494.782919 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.58725983485829384486569858783025734104620787807357012472548153701159196474829
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2851.660924 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2851.660924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4202318715071967614382463359437717877861787883556196402204164659073034857105
    Line 386, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2475.939536 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2475.939536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.71293215703147513659634215408335571280390117403622029086132172276072684982039
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2442.671155 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2442.671155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32599) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.74220634982413929428499277971452015583187951377717738438953092706017142907222
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2194.860100 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32599) { a_addr: 'h1066c  a_data: 'h56e3bf92  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h1b6c1  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2194.860100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.19787594744165111093302760970413712185929061884160895153285134813620420658063
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2571.700570 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2571.700570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.39209567246349745290944921574473412374526599423081028233983147677105206880877
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2781.689000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2781.689000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.16637096775606563119388041502100867693185027137856253402697040116127690952350
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3338.706000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3338.706000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.67359830528577480499888712997065358770093306363989197605670841347512588613447
    Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 15818.392768 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 15818.392768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.7749245068407596671074847785694476338507925257266503438477763373151670051296
    Line 441, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3297.352902 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3297.352902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.92879359667887928107646868391186359709595022723110908554159358719213393392232
    Line 440, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.27779786233977157310921066203345276391225521445423689319563365739154585457759
    Line 426, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.21066300212296023419924903404244293514087909299227708328403093757764073605885
    Line 487, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 13846.661995 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 13846.661995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.72785374944243750931193537332469700147697810992324631842957830786094928740226
    Line 462, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 3874.488684 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3874.488684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@214205) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.26845194007386442852453930915240861565643622544728182606636962402279397603181
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5808.313790 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@214205) { a_addr: 'h10650  a_data: 'h81ec0d92  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h4  a_user: 'h19298  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5808.313790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---