ADC_CTRL Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.440s	6.150ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.110s	931.742us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.650s	544.368us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	41.790s	27.637ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.090s	1.074ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.140s	364.227us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.650s	544.368us	1	1	100.00
		adc_ctrl_csr_aliasing	2.090s	1.074ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	5.348m	332.237ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.347m	325.472ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	9.446m	326.535ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.553m	496.921ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	7.595m	255.577ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	10.410m	412.886ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.175m	344.159ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	13.862m	505.107ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.760s	4.226ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	15.410s	24.762ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	32.070s	120.378ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.189m	340.052ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.410s	436.030us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.970s	487.683us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.520s	1.818ms	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.520s	1.818ms	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.110s	931.742us	1	1	100.00
		adc_ctrl_csr_rw	1.650s	544.368us	1	1	100.00
		adc_ctrl_csr_aliasing	2.090s	1.074ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.260s	4.348ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.110s	931.742us	1	1	100.00
		adc_ctrl_csr_rw	1.650s	544.368us	1	1	100.00
		adc_ctrl_csr_aliasing	2.090s	1.074ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.260s	4.348ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	8.000s	4.086ms	1	1	100.00
		adc_ctrl_tl_intg_err	1.810s	5.134ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	1.810s	5.134ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.450s	6.394ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00