CSRNG Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	4.000s	26.664us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	53.835us	1	1	100.00
V1	csr_rw	csrng_csr_rw	3.000s	22.545us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	6.000s	119.334us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	73.260us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	61.171us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	22.545us	1	1	100.00
		csrng_csr_aliasing	5.000s	73.260us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	10.000s	639.038us	0	1	0.00
V2	alerts	csrng_alert	36.000s	2.687ms	1	1	100.00
V2	err	csrng_err	3.000s	37.219us	1	1	100.00
V2	cmds	csrng_cmds	27.000s	1.866ms	1	1	100.00
V2	life cycle	csrng_cmds	27.000s	1.866ms	1	1	100.00
V2	stress_all	csrng_stress_all	3.900m	4.966ms	1	1	100.00
V2	intr_test	csrng_intr_test	3.000s	13.048us	1	1	100.00
V2	alert_test	csrng_alert_test	4.000s	46.222us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	5.000s	40.353us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	5.000s	40.353us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	53.835us	1	1	100.00
		csrng_csr_rw	3.000s	22.545us	1	1	100.00
		csrng_csr_aliasing	5.000s	73.260us	1	1	100.00
		csrng_same_csr_outstanding	4.000s	45.819us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	53.835us	1	1	100.00
		csrng_csr_rw	3.000s	22.545us	1	1	100.00
		csrng_csr_aliasing	5.000s	73.260us	1	1	100.00
		csrng_same_csr_outstanding	4.000s	45.819us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	4.000s	71.864us	1	1	100.00
		csrng_tl_intg_err	5.000s	176.382us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	3.000s	14.113us	1	1	100.00
		csrng_csr_rw	3.000s	22.545us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	36.000s	2.687ms	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	3.900m	4.966ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	36.000s	2.687ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	3.900m	4.966ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	36.000s	2.687ms	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	5.000s	176.382us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
		csrng_sec_cm	4.000s	71.864us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	639.038us	0	1	0.00
		csrng_err	3.000s	37.219us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.667m	3.322ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 1 failures:
  • Test csrng_intr has 1 failures.

    • 0.csrng_intr.24556760179406785685634381595992048045601956951767772918735321212154076140044
      Line 134, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

        UVM_FATAL @ 639038202 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 639038202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---