EDN Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.840s	31.236us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.780s	26.284us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.850s	18.454us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.570s	82.624us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.180s	41.752us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.210s	22.642us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.850s	18.454us	1	1	100.00
		edn_csr_aliasing	1.180s	41.752us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.400s	199.906us	1	1	100.00
V2	csrng_commands	edn_genbits	1.400s	199.906us	1	1	100.00
V2	genbits	edn_genbits	1.400s	199.906us	1	1	100.00
V2	interrupts	edn_intr	0.920s	24.358us	1	1	100.00
V2	alerts	edn_alert	1.040s	42.186us	1	1	100.00
V2	errs	edn_err	0.850s	28.710us	1	1	100.00
V2	disable	edn_disable	1.000s	35.528us	1	1	100.00
		edn_disable_auto_req_mode	1.230s	54.706us	1	1	100.00
V2	stress_all	edn_stress_all	0.990s	49.310us	1	1	100.00
V2	intr_test	edn_intr_test	0.850s	68.996us	1	1	100.00
V2	alert_test	edn_alert_test	0.830s	20.480us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.560s	99.197us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.560s	99.197us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.780s	26.284us	1	1	100.00
		edn_csr_rw	0.850s	18.454us	1	1	100.00
		edn_csr_aliasing	1.180s	41.752us	1	1	100.00
		edn_same_csr_outstanding	1.160s	616.544us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.780s	26.284us	1	1	100.00
		edn_csr_rw	0.850s	18.454us	1	1	100.00
		edn_csr_aliasing	1.180s	41.752us	1	1	100.00
		edn_same_csr_outstanding	1.160s	616.544us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.850s	523.199us	1	1	100.00
		edn_tl_intg_err	1.960s	193.615us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.100s	54.916us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.040s	42.186us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.850s	523.199us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.850s	523.199us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.850s	523.199us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.850s	523.199us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.040s	42.186us	1	1	100.00
		edn_sec_cm	3.850s	523.199us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.040s	42.186us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.960s	193.615us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.287m	8.751ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00