HMAC Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.970s 377.113us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.910s 90.790us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.810s 29.460us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.870s 382.962us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.290s 317.268us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.140s 55.085us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.810s 29.460us 1 1 100.00
hmac_csr_aliasing 2.290s 317.268us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 3.870s 445.534us 1 1 100.00
V2 back_pressure hmac_back_pressure 2.630s 250.653us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.159m 25.449ms 1 1 100.00
hmac_test_sha384_vectors 19.870s 279.854us 1 1 100.00
hmac_test_sha512_vectors 5.313m 38.266ms 1 1 100.00
hmac_test_hmac256_vectors 7.690s 236.351us 1 1 100.00
hmac_test_hmac384_vectors 6.890s 476.323us 1 1 100.00
hmac_test_hmac512_vectors 9.200s 287.472us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.250s 862.023us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.264m 2.312ms 1 1 100.00
V2 error hmac_error 16.690s 6.458ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.319m 12.715ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.970s 377.113us 1 1 100.00
hmac_long_msg 3.870s 445.534us 1 1 100.00
hmac_back_pressure 2.630s 250.653us 1 1 100.00
hmac_datapath_stress 1.264m 2.312ms 1 1 100.00
hmac_burst_wr 17.250s 862.023us 1 1 100.00
hmac_stress_all 2.641m 61.811ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.970s 377.113us 1 1 100.00
hmac_long_msg 3.870s 445.534us 1 1 100.00
hmac_back_pressure 2.630s 250.653us 1 1 100.00
hmac_datapath_stress 1.264m 2.312ms 1 1 100.00
hmac_wipe_secret 1.319m 12.715ms 1 1 100.00
hmac_test_sha256_vectors 3.159m 25.449ms 1 1 100.00
hmac_test_sha384_vectors 19.870s 279.854us 1 1 100.00
hmac_test_sha512_vectors 5.313m 38.266ms 1 1 100.00
hmac_test_hmac256_vectors 7.690s 236.351us 1 1 100.00
hmac_test_hmac384_vectors 6.890s 476.323us 1 1 100.00
hmac_test_hmac512_vectors 9.200s 287.472us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.970s 377.113us 1 1 100.00
hmac_long_msg 3.870s 445.534us 1 1 100.00
hmac_back_pressure 2.630s 250.653us 1 1 100.00
hmac_datapath_stress 1.264m 2.312ms 1 1 100.00
hmac_burst_wr 17.250s 862.023us 1 1 100.00
hmac_error 16.690s 6.458ms 1 1 100.00
hmac_wipe_secret 1.319m 12.715ms 1 1 100.00
hmac_test_sha256_vectors 3.159m 25.449ms 1 1 100.00
hmac_test_sha384_vectors 19.870s 279.854us 1 1 100.00
hmac_test_sha512_vectors 5.313m 38.266ms 1 1 100.00
hmac_test_hmac256_vectors 7.690s 236.351us 1 1 100.00
hmac_test_hmac384_vectors 6.890s 476.323us 1 1 100.00
hmac_test_hmac512_vectors 9.200s 287.472us 1 1 100.00
hmac_stress_all 2.641m 61.811ms 1 1 100.00
V2 stress_all hmac_stress_all 2.641m 61.811ms 1 1 100.00
V2 alert_test hmac_alert_test 0.770s 28.791us 1 1 100.00
V2 intr_test hmac_intr_test 0.540s 87.790us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.010s 173.092us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.010s 173.092us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.910s 90.790us 1 1 100.00
hmac_csr_rw 0.810s 29.460us 1 1 100.00
hmac_csr_aliasing 2.290s 317.268us 1 1 100.00
hmac_same_csr_outstanding 1.330s 122.295us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.910s 90.790us 1 1 100.00
hmac_csr_rw 0.810s 29.460us 1 1 100.00
hmac_csr_aliasing 2.290s 317.268us 1 1 100.00
hmac_same_csr_outstanding 1.330s 122.295us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.880s 97.993us 1 1 100.00
hmac_tl_intg_err 3.060s 311.350us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.060s 311.350us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.970s 377.113us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.160s 41.465us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 6.257m 30.129ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.870s 8.607us 1 1 100.00
TOTAL 28 28 100.00