I2C Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	20.270s	7.772ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.010s	718.438us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.680s	49.257us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.670s	33.771us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.850s	389.736us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.490s	403.211us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.700s	72.812us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.670s	33.771us	1	1	100.00
		i2c_csr_aliasing	1.490s	403.211us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.950s	15.319us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	8.343m	60.108ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	25.500s	12.341ms	1	1	100.00
V2	host_override	i2c_host_override	0.780s	46.913us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.062m	44.553ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	43.820s	8.420ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.160s	1.842ms	1	1	100.00
		i2c_host_fifo_fmt_empty	9.990s	878.126us	1	1	100.00
		i2c_host_fifo_reset_rx	4.650s	242.205us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	50.260s	8.737ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.850s	853.517us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.690s	5.939us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.470s	1.002ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	26.990s	137.374ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.000s	1.985ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	19.570s	3.347ms	1	1	100.00
		i2c_target_intr_smoke	6.160s	5.636ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.420s	248.146us	1	1	100.00
		i2c_target_fifo_reset_tx	0.950s	198.525us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	41.640s	30.670ms	1	1	100.00
		i2c_target_stress_rd	19.570s	3.347ms	1	1	100.00
		i2c_target_intr_stress_wr	4.960s	8.511ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.670s	1.400ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.100s	2.389ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.920s	1.664ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	4.990s	10.927ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.150s	1.845ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.900s	81.034us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	25.500s	12.341ms	1	1	100.00
		i2c_host_perf_precise	1.407m	24.592ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.850s	853.517us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.220s	51.491us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.760s	448.034us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.810s	1.625ms	1	1	100.00
		i2c_target_nack_txstretch	1.270s	534.322us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.450s	896.866us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.720s	464.847us	1	1	100.00
V2	alert_test	i2c_alert_test	0.690s	38.004us	1	1	100.00
V2	intr_test	i2c_intr_test	0.740s	33.619us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.690s	301.239us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.690s	301.239us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.680s	49.257us	1	1	100.00
		i2c_csr_rw	0.670s	33.771us	1	1	100.00
		i2c_csr_aliasing	1.490s	403.211us	1	1	100.00
		i2c_same_csr_outstanding	1.260s	54.698us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.680s	49.257us	1	1	100.00
		i2c_csr_rw	0.670s	33.771us	1	1	100.00
		i2c_csr_aliasing	1.490s	403.211us	1	1	100.00
		i2c_same_csr_outstanding	1.260s	54.698us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	2.300s	523.296us	1	1	100.00
		i2c_sec_cm	0.770s	125.109us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.300s	523.296us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.280s	510.595us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.390s	211.866us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	13.490s	2.009ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.38029299046037768632771200933752537947635712923024599993724955957695075423350
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  15318932 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  15318932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.3505230603246986355885906100413978751875169787542348467390274463390151653273
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @   5938662 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @   5938662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.49910406636340179972887925173580848087602543558662302772765891134401969452935
      Line 88, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 510595279 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 510595279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.87296067507098071170272346525818896949883594097581423529961344686412808880702
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2009192411 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2009192411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.8144282300331317442727215771642657953149530301284644523740238185862445913368
      Line 119, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 60108004131 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @192334
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.80212774994971056804022329381557313494948808145840128464758352345426258093193
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1002428946 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1002428946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.17901150643517298952236780441322062409223764847718451501954112008019141772397
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 211866496 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 211866496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.90628015433318819423173483384298202571393246247039926002924992360972101608212
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10926818834 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10926818834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---