KMAC/MASKED Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	28.660s	1.304ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.990s	90.769us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.880s	19.278us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.060s	1.970ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.800s	507.435us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.530s	81.680us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.880s	19.278us	1	1	100.00
		kmac_csr_aliasing	3.800s	507.435us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.830s	13.994us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	138.058us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	36.935m	86.814ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.910s	985.188us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.980s	6.173ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.473m	59.915ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.170s	14.169ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.810s	638.471us	1	1	100.00
		kmac_test_vectors_shake_128	2.657m	41.330ms	1	1	100.00
		kmac_test_vectors_shake_256	32.701m	89.168ms	1	1	100.00
		kmac_test_vectors_kmac	3.000s	158.164us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.410s	143.107us	1	1	100.00
V2	sideload	kmac_sideload	4.931m	19.974ms	1	1	100.00
V2	app	kmac_app	16.220s	583.972us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.798m	26.525ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.547m	42.449ms	1	1	100.00
V2	error	kmac_error	31.750s	575.267us	1	1	100.00
V2	key_error	kmac_key_error	4.900s	2.078ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.100s	292.078us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.020s	17.147us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.990s	279.411us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	12.020s	1.464ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.470s	89.813us	1	1	100.00
V2	stress_all	kmac_stress_all	1.480s	342.381us	0	1	0.00
V2	intr_test	kmac_intr_test	0.930s	22.773us	1	1	100.00
V2	alert_test	kmac_alert_test	0.980s	16.071us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.380s	194.434us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.380s	194.434us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.990s	90.769us	1	1	100.00
		kmac_csr_rw	0.880s	19.278us	1	1	100.00
		kmac_csr_aliasing	3.800s	507.435us	1	1	100.00
		kmac_same_csr_outstanding	1.500s	104.552us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.990s	90.769us	1	1	100.00
		kmac_csr_rw	0.880s	19.278us	1	1	100.00
		kmac_csr_aliasing	3.800s	507.435us	1	1	100.00
		kmac_same_csr_outstanding	1.500s	104.552us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.310s	242.158us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.310s	242.158us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.310s	242.158us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.310s	242.158us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.210s	229.546us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	30.060s	6.887ms	1	1	100.00
		kmac_tl_intg_err	2.180s	67.414us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.180s	67.414us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.470s	89.813us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	28.660s	1.304ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.931m	19.974ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.310s	242.158us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	30.060s	6.887ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	30.060s	6.887ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	30.060s	6.887ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	28.660s	1.304ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.470s	89.813us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	30.060s	6.887ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.732m	30.841ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	28.660s	1.304ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	35.540s	1.821ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_stress_all has 1 failures.

    • 0.kmac_stress_all.13769407899686661436921120591287671618216310028265835956452904839847038468809
      Line 77, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log

        UVM_ERROR @ 342381452 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 342381452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---