KMAC/UNMASKED Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	13.860s	382.404us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.960s	36.609us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.120s	41.890us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.210s	981.220us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.310s	916.714us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.090s	72.291us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.120s	41.890us	1	1	100.00
		kmac_csr_aliasing	4.310s	916.714us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.970s	36.038us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.550s	135.133us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	10.323m	104.791ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.564m	8.279ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.010s	28.675ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.268m	59.257ms	1	1	100.00
		kmac_test_vectors_sha3_384	26.170s	3.354ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.280s	2.868ms	1	1	100.00
		kmac_test_vectors_shake_128	24.001m	80.225ms	1	1	100.00
		kmac_test_vectors_shake_256	18.967m	61.300ms	1	1	100.00
		kmac_test_vectors_kmac	1.580s	80.624us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.620s	393.668us	1	1	100.00
V2	sideload	kmac_sideload	1.177m	5.129ms	1	1	100.00
V2	app	kmac_app	1.974m	3.479ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	14.570s	2.268ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.758m	29.053ms	1	1	100.00
V2	error	kmac_error	4.579m	77.925ms	1	1	100.00
V2	key_error	kmac_key_error	9.320s	4.491ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.610m	10.085ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	3.920s	361.570us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	5.900s	223.759us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	41.490s	23.162ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	12.240s	282.021us	1	1	100.00
V2	stress_all	kmac_stress_all	13.146m	168.409ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.900s	54.909us	1	1	100.00
V2	alert_test	kmac_alert_test	0.870s	17.053us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.130s	296.842us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.130s	296.842us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.960s	36.609us	1	1	100.00
		kmac_csr_rw	1.120s	41.890us	1	1	100.00
		kmac_csr_aliasing	4.310s	916.714us	1	1	100.00
		kmac_same_csr_outstanding	1.270s	39.624us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.960s	36.609us	1	1	100.00
		kmac_csr_rw	1.120s	41.890us	1	1	100.00
		kmac_csr_aliasing	4.310s	916.714us	1	1	100.00
		kmac_same_csr_outstanding	1.270s	39.624us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.820s	114.103us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.820s	114.103us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.820s	114.103us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.820s	114.103us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.590s	158.319us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	20.180s	2.253ms	1	1	100.00
		kmac_tl_intg_err	3.110s	104.052us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.110s	104.052us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	12.240s	282.021us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	13.860s	382.404us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.177m	5.129ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.820s	114.103us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	20.180s	2.253ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	20.180s	2.253ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	20.180s	2.253ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	13.860s	382.404us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	12.240s	282.021us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	20.180s	2.253ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.178m	4.181ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	13.860s	382.404us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	19.910s	4.209ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.80265023669294432742350122928287900796118581809601544241995139217151320224542
      Line 83, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10085355615 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7d4a3000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
        UVM_INFO @ 10085355615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.64386642933729949523400841488930786088069555612544514484991981329782636327693
      Line 92, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4208564662 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4208564662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---