OTBN Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 13.000s 45.375us 0 1 0.00
V1 single_binary otbn_single 8.000s 17.398us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 27.867us 1 1 100.00
V1 csr_rw otbn_csr_rw 6.000s 17.483us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 31.629us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 31.009us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 233.161us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 17.483us 1 1 100.00
otbn_csr_aliasing 4.000s 31.009us 1 1 100.00
V1 mem_walk otbn_mem_walk 31.000s 365.632us 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 15.000s 363.401us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 15.000s 118.421us 0 1 0.00
V2 multi_error otbn_multi_err 42.000s 338.809us 0 1 0.00
V2 back_to_back otbn_multi 15.000s 37.862us 0 1 0.00
V2 stress_all otbn_stress_all 25.000s 191.968us 0 1 0.00
V2 lc_escalation otbn_escalate 8.000s 68.018us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 5.000s 13.799us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 8.000s 23.950us 0 1 0.00
V2 alert_test otbn_alert_test 5.000s 56.243us 1 1 100.00
V2 intr_test otbn_intr_test 4.000s 46.060us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 76.732us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 76.732us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 27.867us 1 1 100.00
otbn_csr_rw 6.000s 17.483us 1 1 100.00
otbn_csr_aliasing 4.000s 31.009us 1 1 100.00
otbn_same_csr_outstanding 5.000s 26.606us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 27.867us 1 1 100.00
otbn_csr_rw 6.000s 17.483us 1 1 100.00
otbn_csr_aliasing 4.000s 31.009us 1 1 100.00
otbn_same_csr_outstanding 5.000s 26.606us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 10.000s 27.690us 0 1 0.00
otbn_dmem_err 6.000s 13.706us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 8.000s 28.649us 0 1 0.00
otbn_controller_ispr_rdata_err 8.000s 44.633us 0 1 0.00
otbn_mac_bignum_acc_err 15.000s 45.386us 0 1 0.00
otbn_urnd_err 9.000s 35.147us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 17.606us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 31.183us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 47.462us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 8.083m 2.905ms 1 1 100.00
otbn_tl_intg_err 10.000s 249.935us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 12.000s 204.893us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 13.000s 45.375us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 6.000s 13.706us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 27.690us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 10.000s 249.935us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 68.018us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 27.690us 0 1 0.00
otbn_dmem_err 6.000s 13.706us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 13.799us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.606us 1 1 100.00
otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 27.690us 0 1 0.00
otbn_dmem_err 6.000s 13.706us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 13.799us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.606us 1 1 100.00
otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 68.018us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 27.690us 0 1 0.00
otbn_dmem_err 6.000s 13.706us 0 1 0.00
otbn_zero_state_err_urnd 5.000s 13.799us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.606us 1 1 100.00
otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 12.704us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 12.535us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 16.000s 90.089us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 16.000s 90.089us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 9.000s 19.961us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 9.000s 111.085us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 24.837us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 24.837us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 7.000s 29.646us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 15.000s 37.862us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 8.000s 61.072us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 8.000s 17.398us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 8.083m 2.905ms 1 1 100.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 2.600m 844.211us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets