PATTGEN Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	3.000s	64.850us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	15.001us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	57.042us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	73.376us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	21.479us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	35.203us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	57.042us	1	1	100.00
		pattgen_csr_aliasing	2.000s	21.479us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	3.067m	191.107ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	15.000s	5.976ms	1	1	100.00
V2	error	pattgen_error	3.000s	41.141us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	2.000s	44.078us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	12.049us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	336.493us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	336.493us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	15.001us	1	1	100.00
		pattgen_csr_rw	2.000s	57.042us	1	1	100.00
		pattgen_csr_aliasing	2.000s	21.479us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	46.067us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	15.001us	1	1	100.00
		pattgen_csr_rw	2.000s	57.042us	1	1	100.00
		pattgen_csr_aliasing	2.000s	21.479us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	46.067us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	81.646us	1	1	100.00
		pattgen_sec_cm	3.000s	147.678us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	81.646us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	24.000s	7.963ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	3.000s	82.800us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.66013047358044680605959458785890650385174619057579875563338766017969236498343
      Line 138, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3358696122 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 3358706417 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3358706417 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 2/5
        UVM_INFO @ 3358866417 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• Job timed out after * minutes has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.44851720240754030543879273813657475841399709045433636695478101111524781149611
      Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        Job timed out after 180 minutes