ROM_CTRL/64KB Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.240s	1.092ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.350s	303.227us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.120s	2.098ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.430s	1.025ms	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.250s	302.593us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	9.510s	303.769us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.120s	2.098ms	1	1	100.00
		rom_ctrl_csr_aliasing	8.250s	302.593us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.990s	990.078us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.460s	1.068ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.660s	1.842ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	25.690s	764.541us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.060s	723.765us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	6.410s	205.581us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.140s	210.574us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.140s	210.574us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.350s	303.227us	1	1	100.00
		rom_ctrl_csr_rw	7.120s	2.098ms	1	1	100.00
		rom_ctrl_csr_aliasing	8.250s	302.593us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.310s	211.837us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.350s	303.227us	1	1	100.00
		rom_ctrl_csr_rw	7.120s	2.098ms	1	1	100.00
		rom_ctrl_csr_aliasing	8.250s	302.593us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.310s	211.837us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	23.730s	761.412us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.477m	1.104ms	0	1	0.00
		rom_ctrl_tl_intg_err	1.508m	1.604ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.477m	1.104ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.477m	1.104ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.477m	1.104ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.477m	1.104ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.240s	1.092ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.240s	1.092ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.240s	1.092ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.508m	1.604ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
		rom_ctrl_kmac_err_chk	12.060s	723.765us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.907m	13.895ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	23.730s	761.412us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.477m	1.104ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.978m	8.822ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.27086998330864003337298908514368171711875382510797001231661659315078635416283
      Line 484, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 110538371ps failed at 110538371ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 110558779ps failed at 110558779ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'