| V1 |
random |
rv_timer_random |
0.690s |
13.559us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
0.690s |
17.555us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
0.560s |
13.292us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
1.720s |
371.820us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
0.610s |
20.249us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
0.740s |
21.251us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
0.560s |
13.292us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.610s |
20.249us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
0.910s |
160.340us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.990s |
1.387ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
2.150m |
412.622ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
2.150m |
412.622ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
1.740s |
2.382ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
0.550s |
17.371us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
0.610s |
14.841us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.160s |
166.182us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.160s |
166.182us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
0.690s |
17.555us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.560s |
13.292us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.610s |
20.249us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.830s |
28.858us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
0.690s |
17.555us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.560s |
13.292us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.610s |
20.249us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.830s |
28.858us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
0.740s |
681.343us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
0.940s |
87.898us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
0.940s |
87.898us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
0.710s |
44.313us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
0.630s |
44.220us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
26.850s |
4.307ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |