SPI_DEVICE/1R1W Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	48.240s	18.698ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.310s	34.570us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.730s	97.471us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.910s	741.184us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.360s	1.241ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.810s	41.229us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.730s	97.471us	1	1	100.00
		spi_device_csr_aliasing	10.360s	1.241ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.810s	11.362us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.650s	24.712us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.810s	22.459us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.820s	3.901us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.860s	4.757us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.210s	17.545us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.210s	17.545us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	7.910s	2.432ms	1	1	100.00
		spi_device_tpm_sts_read	0.800s	14.602us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.370s	1.966ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.490s	4.716ms	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.890s	667.784us	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.890s	667.784us	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.910s	230.248us	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.910s	230.248us	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.910s	230.248us	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.910s	230.248us	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.910s	230.248us	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.000s	11.891ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	36.600s	5.100ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	36.600s	5.100ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	36.600s	5.100ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	27.070s	13.156ms	1	1	100.00
		spi_device_read_buffer_direct	2.960s	77.060us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	36.600s	5.100ms	1	1	100.00
		spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.858m	144.469ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.700s	57.055us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.700s	57.055us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	48.240s	18.698ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	17.620s	1.202ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.764m	204.966ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.880s	34.995us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.790s	56.890us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.350s	89.484us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.350s	89.484us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.310s	34.570us	1	1	100.00
		spi_device_csr_rw	1.730s	97.471us	1	1	100.00
		spi_device_csr_aliasing	10.360s	1.241ms	1	1	100.00
		spi_device_same_csr_outstanding	3.150s	57.357us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.310s	34.570us	1	1	100.00
		spi_device_csr_rw	1.730s	97.471us	1	1	100.00
		spi_device_csr_aliasing	10.360s	1.241ms	1	1	100.00
		spi_device_same_csr_outstanding	3.150s	57.357us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.620s	309.582us	1	1	100.00
		spi_device_tl_intg_err	9.180s	897.727us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.180s	897.727us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.750s	382.562us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.101437558577306177677816954760131962733116374396013665204122542316691887847189
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3150743 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[33])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3150743 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3150743 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[929])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.50357440872713530591015918950538397604427370472191964304767223470755129865430
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2337259 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6009ce [11000000000100111001110] vs 0x0 [0])
        UVM_ERROR @   2422259 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3895a9 [1110001001010110101001] vs 0x0 [0])
        UVM_ERROR @   2462259 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf6cd5 [11110110110011010101] vs 0x0 [0])
        UVM_ERROR @   2500259 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x713031 [11100010011000000110001] vs 0x0 [0])
        UVM_ERROR @   2539259 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x22a9ae [1000101010100110101110] vs 0x0 [0])