SPI_DEVICE/2P Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	20.500s	15.685ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.130s	20.562us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.570s	53.852us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.480s	7.229ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.200s	325.496us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.810s	254.007us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.570s	53.852us	1	1	100.00
		spi_device_csr_aliasing	6.200s	325.496us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	42.620us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.390s	53.162us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.980s	17.159us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.300s	32.581us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	17.263us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.440s	174.506us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.440s	174.506us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.590s	2.113ms	1	1	100.00
		spi_device_tpm_sts_read	0.890s	22.782us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	21.770s	5.893ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.750s	1.025ms	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.570s	241.953us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.570s	241.953us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.520s	719.517us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.520s	719.517us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.520s	719.517us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.520s	719.517us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.520s	719.517us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	18.460s	8.225ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.180s	98.950us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.180s	98.950us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.180s	98.950us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	11.860s	4.453ms	1	1	100.00
		spi_device_read_buffer_direct	9.990s	22.096ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.180s	98.950us	1	1	100.00
		spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.087m	124.392ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.320s	3.532ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.320s	3.532ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	20.500s	15.685ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	38.120s	9.109ms	1	1	100.00
V2	stress_all	spi_device_stress_all	50.670s	3.771ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.820s	21.607us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.770s	12.353us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.760s	61.353us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.760s	61.353us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.130s	20.562us	1	1	100.00
		spi_device_csr_rw	1.570s	53.852us	1	1	100.00
		spi_device_csr_aliasing	6.200s	325.496us	1	1	100.00
		spi_device_same_csr_outstanding	2.080s	43.310us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.130s	20.562us	1	1	100.00
		spi_device_csr_rw	1.570s	53.852us	1	1	100.00
		spi_device_csr_aliasing	6.200s	325.496us	1	1	100.00
		spi_device_same_csr_outstanding	2.080s	43.310us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.510s	98.545us	1	1	100.00
		spi_device_tl_intg_err	16.170s	1.038ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.170s	1.038ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.674m	143.233ms	1	1	100.00
		TOTAL			33	33	100.00