SRAM_CTRL/MAIN Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.930s	1.589ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	14.037us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.860s	17.443us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.120s	72.153us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	28.365us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.730s	354.955us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.860s	17.443us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	28.365us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.177m	18.508ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.488m	6.638ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.882m	18.291ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.712m	4.250ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	9.276m	45.151ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.170m	12.881ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.302m	180.958ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.663m	19.739ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.860s	1.390ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.274m	24.800ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.130s	4.731ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.010s	2.668ms	1	1	100.00
		sram_ctrl_throughput_w_readback	1.059m	7.026ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.890m	20.855ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.970s	1.346ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	12.710m	23.005ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.840s	12.681us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.130s	46.029us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.130s	46.029us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	14.037us	1	1	100.00
		sram_ctrl_csr_rw	0.860s	17.443us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	28.365us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	52.330us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	14.037us	1	1	100.00
		sram_ctrl_csr_rw	0.860s	17.443us	1	1	100.00
		sram_ctrl_csr_aliasing	0.720s	28.365us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	52.330us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.730s	3.839ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.730s	8.256us	0	1	0.00
		sram_ctrl_tl_intg_err	1.650s	218.134us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.730s	8.256us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.650s	218.134us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.890m	20.855ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.890m	20.855ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.860s	17.443us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.663m	19.739ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.663m	19.739ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.663m	19.739ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.302m	180.958ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.290s	4.441ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.730s	3.839ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.880s	2.898ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.930s	1.589ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.930s	1.589ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.663m	19.739ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.730s	8.256us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.302m	180.958ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.730s	8.256us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.730s	8.256us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.930s	1.589ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.730s	8.256us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.590s	3.590ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.14777941604264671618303201787636337577042994376305531708594586760893724991060
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8255848 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8255848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---