SRAM_CTRL/RET Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.820s	129.922us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.910s	16.879us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.860s	15.025us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.330s	73.611us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.930s	55.578us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.450s	666.696us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.860s	15.025us	1	1	100.00
		sram_ctrl_csr_aliasing	0.930s	55.578us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.550s	526.754us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.710s	99.777us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.746m	1.377ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.847m	1.623ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	26.690s	2.263ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.594m	8.128ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.290s	387.821us	1	1	100.00
V2	executable	sram_ctrl_executable	5.241m	13.593ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	30.790s	972.340us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.540m	32.199ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.540s	580.354us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	29.210s	509.788us	1	1	100.00
		sram_ctrl_throughput_w_readback	45.680s	580.546us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.257m	15.125ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.720s	34.519us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	17.417m	11.538ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.660s	13.336us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.200s	34.466us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.200s	34.466us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.910s	16.879us	1	1	100.00
		sram_ctrl_csr_rw	0.860s	15.025us	1	1	100.00
		sram_ctrl_csr_aliasing	0.930s	55.578us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.820s	15.601us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.910s	16.879us	1	1	100.00
		sram_ctrl_csr_rw	0.860s	15.025us	1	1	100.00
		sram_ctrl_csr_aliasing	0.930s	55.578us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.820s	15.601us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.730s	718.363us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.720s	7.831us	0	1	0.00
		sram_ctrl_tl_intg_err	1.520s	522.686us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.720s	7.831us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.520s	522.686us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.257m	15.125ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.257m	15.125ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.860s	15.025us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.241m	13.593ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.241m	13.593ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.241m	13.593ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.290s	387.821us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.070s	35.957us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.730s	718.363us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.010s	24.413us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.820s	129.922us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.820s	129.922us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.241m	13.593ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.720s	7.831us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.290s	387.821us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.720s	7.831us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.720s	7.831us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.820s	129.922us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.720s	7.831us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	43.860s	1.735ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.77126109162220776435559634804561944225701666020219589323463317578245100635479
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  24413328 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xe) != exp (0x43)
        UVM_INFO @  24413328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.58211676427115402635314663337407981209665106113761585302027213924021251109751
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7831249 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7831249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---