SYSRST_CTRL Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.440s 2.128ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.240s 2.450ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 1.660s 2.219ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.570s 2.557ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.980s 4.036ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 1.650s 2.078ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 26.370s 39.056ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 8.020s 2.806ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.930s 2.047ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.650s 2.078ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.020s 2.806ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.903m 124.888ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 26.840s 55.099ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.520s 3.480ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 3.520s 5.093ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 3.000s 2.519ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.720s 2.078ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.260s 3.144ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.050s 2.634ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 7.580s 11.912ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 19.410s 41.776ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 1.440m 49.753ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 1.680s 2.047ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.700s 2.038ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 4.580s 2.023ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 4.580s 2.023ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.980s 4.036ms 1 1 100.00
sysrst_ctrl_csr_rw 1.650s 2.078ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.020s 2.806ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.050s 7.792ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.980s 4.036ms 1 1 100.00
sysrst_ctrl_csr_rw 1.650s 2.078ms 1 1 100.00
sysrst_ctrl_csr_aliasing 8.020s 2.806ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.050s 7.792ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.325m 42.011ms 1 1 100.00
sysrst_ctrl_tl_intg_err 46.180s 22.208ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 46.180s 22.208ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 8.790s 4.239ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00