UART Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: 8a6efc3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.750s	446.068us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.580s	15.748us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.610s	44.298us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.860s	339.159us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.840s	98.660us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.660s	37.888us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.610s	44.298us	1	1	100.00
		uart_csr_aliasing	0.840s	98.660us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.618m	139.370ms	1	1	100.00
V2	parity	uart_smoke	1.750s	446.068us	1	1	100.00
		uart_tx_rx	1.618m	139.370ms	1	1	100.00
V2	parity_error	uart_intr	6.320s	43.703ms	1	1	100.00
		uart_rx_parity_err	1.494m	101.849ms	1	1	100.00
V2	watermark	uart_tx_rx	1.618m	139.370ms	1	1	100.00
		uart_intr	6.320s	43.703ms	1	1	100.00
V2	fifo_full	uart_fifo_full	12.730s	48.625ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	12.780s	134.455ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.856m	141.528ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.320s	43.703ms	1	1	100.00
V2	rx_break_err	uart_intr	6.320s	43.703ms	1	1	100.00
V2	rx_timeout	uart_intr	6.320s	43.703ms	1	1	100.00
V2	perf	uart_perf	5.690m	9.308ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.760s	6.810ms	1	1	100.00
V2	line_loopback	uart_loopback	5.760s	6.810ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.830s	21.861ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.960s	3.042ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.970s	897.668us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	23.140s	3.982ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.231m	157.328ms	1	1	100.00
V2	stress_all	uart_stress_all	1.090m	371.683ms	1	1	100.00
V2	alert_test	uart_alert_test	0.690s	11.964us	1	1	100.00
V2	intr_test	uart_intr_test	0.690s	13.824us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.140s	102.564us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.140s	102.564us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.580s	15.748us	1	1	100.00
		uart_csr_rw	0.610s	44.298us	1	1	100.00
		uart_csr_aliasing	0.840s	98.660us	1	1	100.00
		uart_same_csr_outstanding	0.760s	59.754us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.580s	15.748us	1	1	100.00
		uart_csr_rw	0.610s	44.298us	1	1	100.00
		uart_csr_aliasing	0.840s	98.660us	1	1	100.00
		uart_same_csr_outstanding	0.760s	59.754us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.770s	35.834us	1	1	100.00
		uart_tl_intg_err	0.940s	196.537us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.940s	196.537us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.370s	15.932ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.93740520376901487187880542846635188756236996812914976505818504473827367684880
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 20718758944 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 20718758944 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 20768084735 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 20768149952 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 20768171691 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (116 [0x74] vs 255 [0xff]) reg name: uart_reg_block.rdata