CHIP Simulation Results

Wednesday September 10 2025 20:55:02 UTC

GitHub Revision: `8a6efc3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.042m	2.813ms	1	1	100.00
		chip_sw_example_rom	54.430s	2.227ms	1	1	100.00
		chip_sw_example_manufacturer	1.963m	2.723ms	1	1	100.00
		chip_sw_example_concurrency	2.400m	2.535ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.743m	5.222ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.122m	6.394ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.142m	4.185ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.224h	38.679ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	7.978m	10.559ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.224h	38.679ms	1	1	100.00
		chip_csr_rw	6.122m	6.394ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.490s	45.302us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.949m	4.200ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.949m	4.200ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.949m	4.200ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.204m	4.658ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.204m	4.658ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.608m	3.781ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.538m	4.533ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.542m	4.717ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.485m	3.209ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.390m	8.411ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.165m	4.027ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	3.409m	5.038ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.409m	5.038ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.743m	3.265ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.317m	2.539ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.996m	3.678ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.411m	2.082ms	1	1	100.00
		chip_tap_straps_testunlock0	7.360m	6.701ms	1	1	100.00
		chip_tap_straps_rma	5.083m	5.775ms	1	1	100.00
		chip_tap_straps_prod	1.473m	2.415ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.802m	2.206ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.003m	9.216ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.455m	5.929ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.455m	5.929ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.186m	7.834ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	36.616m	23.264ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.947m	3.904ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.696m	5.569ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.929m	18.420ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.074m	3.428ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.454m	6.273ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.609m	3.119ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.492m	12.957ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.751m	2.702ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.524m	4.401ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.096m	3.031ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.274m	2.969ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.018m	7.437ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.421m	4.608ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.236m	2.688ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.421m	4.608ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.951m	2.436ms	1	1	100.00
		chip_sw_aes_smoketest	2.712m	2.410ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.872m	3.253ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.386m	3.187ms	1	1	100.00
		chip_sw_csrng_smoketest	1.987m	2.721ms	1	1	100.00
		chip_sw_entropy_src_smoketest	11.618m	6.861ms	1	1	100.00
		chip_sw_gpio_smoketest	2.784m	3.637ms	1	1	100.00
		chip_sw_hmac_smoketest	2.939m	3.200ms	1	1	100.00
		chip_sw_kmac_smoketest	3.425m	3.550ms	1	1	100.00
		chip_sw_otbn_smoketest	9.756m	5.587ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.157m	5.748ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.452m	5.606ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.456m	2.405ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.385m	2.955ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.808m	3.148ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.997m	2.919ms	1	1	100.00
		chip_sw_uart_smoketest	1.959m	3.004ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.599m	2.395ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.576m	4.386ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.086h	62.197ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.160m	14.816ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	3.278m	6.462ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.874m	3.250ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.563m	2.647ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.940h	54.997ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.930h	56.098ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.014m	2.445ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.014m	2.445ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.224h	38.679ms	1	1	100.00
		chip_same_csr_outstanding	37.230m	31.058ms	1	1	100.00
		chip_csr_hw_reset	2.743m	5.222ms	1	1	100.00
		chip_csr_rw	6.122m	6.394ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.224h	38.679ms	1	1	100.00
		chip_same_csr_outstanding	37.230m	31.058ms	1	1	100.00
		chip_csr_hw_reset	2.743m	5.222ms	1	1	100.00
		chip_csr_rw	6.122m	6.394ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	26.120s	1.020ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.980s	50.110us	1	1	100.00
		xbar_smoke_large_delays	51.750s	8.383ms	1	1	100.00
		xbar_smoke_slow_rsp	48.420s	5.415ms	1	1	100.00
		xbar_random_zero_delays	38.740s	461.551us	1	1	100.00
		xbar_random_large_delays	2.050m	20.192ms	1	1	100.00
		xbar_random_slow_rsp	1.162m	7.809ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	28.070s	1.038ms	1	1	100.00
		xbar_error_and_unmapped_addr	12.490s	190.475us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	37.960s	1.531ms	1	1	100.00
		xbar_error_and_unmapped_addr	12.490s	190.475us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	13.080s	478.212us	1	1	100.00
		xbar_access_same_device_slow_rsp	7.086m	48.915ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	28.140s	1.603ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	59.690s	2.718ms	1	1	100.00
		xbar_stress_all_with_error	3.615m	11.928ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.905m	534.314us	1	1	100.00
		xbar_stress_all_with_reset_error	2.805m	976.434us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.160m	14.816ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	40.666m	32.503ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.043m	16.387ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.383m	10.885ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.995m	15.954ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.268m	15.654ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.126m	15.396ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.613m	15.025ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.530s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	23.220s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	23.700s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	19.730s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.360s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.600s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.640s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.940s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.460s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.720s	10.220us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.730s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.440s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.940s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	21.470s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.060s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.370s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.450s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.320s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.500s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.760s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.880s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.210s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.640s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.720s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	24.910s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.675m	11.889ms	1	1	100.00
		rom_e2e_asm_init_dev	41.926m	15.960ms	1	1	100.00
		rom_e2e_asm_init_prod	41.633m	16.040ms	1	1	100.00
		rom_e2e_asm_init_prod_end	42.197m	16.133ms	1	1	100.00
		rom_e2e_asm_init_rma	38.476m	16.351ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.316m	15.130ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.915m	15.239ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.797m	14.829ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.572m	18.186ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.679m	34.904ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.679m	34.904ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.134m	2.509ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.074m	3.428ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.053m	2.611ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.410m	2.325ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	27.913m	13.533ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.105m	3.191ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.996m	5.272ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	7.548m	5.293ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.790m	5.451ms	1	1	100.00
		chip_plic_all_irqs_10	4.733m	3.316ms	1	1	100.00
		chip_plic_all_irqs_20	5.813m	4.459ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.597m	3.341ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.495m	11.152ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.778m	2.853ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.536m	2.936ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.274m	11.079ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.723m	8.628ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.538m	7.242ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.070m	7.936ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.378h	254.293ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.978m	4.311ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.157m	5.748ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.978m	4.311ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.619m	7.420ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.619m	7.420ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.423m	8.371ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.932m	5.418ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.220m	6.508ms	1	1	100.00
		chip_sw_aes_idle	2.410m	2.325ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.354m	3.112ms	1	1	100.00
		chip_sw_kmac_idle	2.227m	2.546ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.876m	4.802ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.598m	4.440ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.785m	5.262ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.700m	5.227ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	15.404m	10.956ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.995m	3.793ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.916m	4.622ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.575m	3.839ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.412m	4.539ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.363m	4.050ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.406m	4.994ms	1	1	100.00
		chip_sw_ast_clk_outputs	11.186m	7.834ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.432m	6.207ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.575m	3.839ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.412m	4.539ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.947m	3.904ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.696m	5.569ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.929m	18.420ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.074m	3.428ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.454m	6.273ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.609m	3.119ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.492m	12.957ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.751m	2.702ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.524m	4.401ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.096m	3.031ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.858m	3.038ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.335m	4.723ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.775m	7.309ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.298m	24.295ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.092m	2.859ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.579m	3.090ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.214m	11.021ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.690m	3.027ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.516m	3.980ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.939m	18.419ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	46.065m	28.794ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.186m	7.834ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.235m	4.538ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.650m	3.576ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	7.548m	5.293ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.723m	8.628ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.100m	6.216ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.749m	3.987ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.325m	5.510ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.487m	2.699ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.130h	26.434ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.169m	3.001ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.605m	6.321ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.169m	3.001ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.100m	6.216ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.572m	3.341ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.272m	18.187ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.603m	5.532ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.696m	5.569ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.728m	4.401ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.947m	3.904ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	59.665m	43.761ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.272m	18.187ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.757m	2.970ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	20.574m	9.112ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.752m	4.869ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	59.665m	43.761ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.752m	4.869ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.752m	4.869ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.752m	4.869ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.752m	4.869ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	7.548m	5.293ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.422m	6.849ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.470m	4.919ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.261m	4.742ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.261m	4.742ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.416m	3.348ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.609m	3.119ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.354m	3.112ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.879m	2.441ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	3.805m	3.795ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.585m	4.888ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.265m	4.716ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.819m	5.199ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.514m	3.918ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	20.574m	9.112ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.492m	12.957ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	19.788m	10.026ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	27.913m	13.533ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	35.466m	11.874ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.603m	2.715ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.599m	2.796ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.751m	2.702ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	20.574m	9.112ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.813m	3.263ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	22.311m	8.691ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.227m	2.546ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.996m	5.272ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.411m	2.082ms	1	1	100.00
		chip_tap_straps_rma	5.083m	5.775ms	1	1	100.00
		chip_tap_straps_prod	1.473m	2.415ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.763m	3.134ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	22.832m	11.387ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.752m	4.869ms	1	1	100.00
		chip_sw_flash_rma_unlocked	59.665m	43.761ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.391m	3.301ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.260m	5.313ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.196m	6.556ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.052m	6.815ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.574m	9.112ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.030m	9.888ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.125m	7.517ms	1	1	100.00
		chip_prim_tl_access	2.422m	6.849ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.432m	6.207ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.995m	3.793ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.916m	4.622ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.575m	3.839ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.412m	4.539ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.363m	4.050ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.406m	4.994ms	1	1	100.00
		chip_tap_straps_dev	1.411m	2.082ms	1	1	100.00
		chip_tap_straps_rma	5.083m	5.775ms	1	1	100.00
		chip_tap_straps_prod	1.473m	2.415ms	1	1	100.00
		chip_rv_dm_lc_disabled	10.066m	19.620ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.264m	3.348ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.433m	3.249ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.626m	3.300ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	31.313m	27.208ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.135m	32.442ms	1	1	100.00
		chip_rv_dm_lc_disabled	10.066m	19.620ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.002h	48.785ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.019h	49.248ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.338m	9.258ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.067h	47.439ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.135m	32.442ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.091m	2.360ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.064m	2.222ms	1	1	100.00
		rom_volatile_raw_unlock	1.092m	2.835ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.968m	16.691ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.929m	18.420ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.220m	6.508ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.220m	6.508ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.220m	6.508ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.120m	3.526ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.272m	18.187ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.120m	3.526ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.574m	9.112ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.783m	5.269ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.298m	3.322ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.272m	18.187ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.120m	3.526ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.574m	9.112ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.783m	5.269ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.298m	3.322ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.539m	4.478ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.763m	3.134ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.391m	3.301ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.260m	5.313ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.196m	6.556ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.052m	6.815ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.572m	7.597ms	1	1	100.00
		chip_prim_tl_access	2.422m	6.849ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.422m	6.849ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.593m	9.268ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.584m	7.530ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	21.050m	27.311ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.862m	7.331ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.259m	9.540ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	8.085m	8.202ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.359m	25.374ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.652m	15.468ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.619m	7.420ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.087m	11.355ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.490m	4.238ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.584m	7.530ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.609m	4.127ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.699m	34.123ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.880m	5.663ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.447m	4.561ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	31.232m	28.053ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.805m	7.158ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.290m	12.147ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	31.038m	29.581ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.098m	2.582ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	7.548m	5.293ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.030m	9.888ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.030m	9.888ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.290m	12.147ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	31.232m	28.053ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.490m	4.238ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.157m	5.748ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.308m	4.656ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.106m	4.599ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.503m	3.251ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.495m	11.152ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.717m	2.914ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	7.548m	5.293ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.538m	7.242ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.699m	4.629ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.886m	4.658ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.249m	2.770ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.298m	3.322ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.106m	4.599ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.106m	4.599ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.936m	12.423ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.854m	13.226ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.308m	4.656ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.329m	5.118ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.558m	5.698ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	5.083m	5.775ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.066m	19.620ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.790m	5.451ms	1	1	100.00
		chip_plic_all_irqs_10	4.733m	3.316ms	1	1	100.00
		chip_plic_all_irqs_20	5.813m	4.459ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.852m	2.575ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.796m	2.406ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.160m	14.816ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.653m	7.521ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.866m	3.401ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.172m	3.704ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.266m	2.091ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.783m	5.269ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.524m	4.401ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.191m	8.237ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.531m	6.314ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.125m	7.517ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	7.548m	5.293ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.455m	5.929ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.805m	7.158ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.526m	21.696ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.103m	3.040ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.584m	3.318ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.219m	3.980ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.526m	21.696ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.526m	21.696ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	10.807m	11.247ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	10.807m	11.247ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	6.074m	5.428ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50.679m	34.904ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.439m	2.522ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.592m	3.100ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.626m	3.375ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.940m	4.545ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.860m	8.059ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.371h	31.346ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.967m	11.684ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.861m	2.584ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.123m	2.983ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.699m	2.525ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.557h	71.834ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.365m	3.853ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.911m	2.991ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.800m	10.463ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.742m	12.527ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.108m	4.587ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.457m	4.553ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.549m	3.465ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.753s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.383m	5.116ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.885m	2.923ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	17.617m	6.588ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.004m	6.441ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.783m	2.222ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.403m	5.323ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.342m	2.898ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.328m	6.376ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.050m	6.481ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.823m	4.492ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.290m	12.147ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.911m	2.991ms	0	1	0.00
		rom_e2e_jtag_debug_dev	18.800m	10.463ms	1	1	100.00
		rom_e2e_jtag_debug_rma	19.742m	12.527ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.357m	6.082ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	7.548m	5.293ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.491h	38.266ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.491h	38.266ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.544m	3.022ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.204m	4.658ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	51.367m	19.000ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.287m	2.496ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.464m	5.437ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.693m	2.578ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.973m	3.665ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.680m	3.635ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.453s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.672m	3.067ms	1	1	100.00
		TOTAL			283	325	87.08

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.70249862341473859207918683142977352992729920286807018288909887898542627682162
    Line 495, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.70632322621773000284843039952209010057424463032648427561172619850320599797348
    Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.28283854054916022196178604888033824810017094379071649810867900860861511134451
    Line 519, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.66296525872736735684308558524864472209505367449270009767583782231642829291487
    Line 533, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.74435756424930960363779121045820012834964582187599780782160728934297927900142
    Line 541, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.39242221277469652501140449940803151754025574850214712531814261031631479054944
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.31531730943824038007223848673428633273290368083630741731225321249808761089686
    Line 487, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.18298327091881460864217590033650025966059621209191364636334242882545638748809
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.111388425752615404576397185963807389695908170207551116353866428168404791029162
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.68872111550217427344343234014290597807266677452900400008785986154067725324193
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.42858614888853450443415104445075916744618665616407101901102644033506995316127
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.98029628891569758126286570255015465117444294962632755918467493906356558535009
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.100487154449938358596708149638988718216719194713389796676418808025795648195942
    Line 533, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.23110639412340461506563170572279899092111616860449405119865805641792893148481
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.162s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.41943335694493808232253696123398492202885714600557414483840886004231254607959
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.165s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.30589553265334684996250401837730551193074989643299484859508207607813537577312
    Line 623, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.110358975845067335815174563968026520921704814186396160331542904291071823445081
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.28186997968843603020748467677289325120708085646232215111689922525656826887538
    Line 604, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.8670771614419292925020965053912722541293312795849518422020442996166608502584
    Line 594, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.15082379751236502795703946166637826418059812890515703173519524386649042927364
    Line 584, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3265.223500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3265.223500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.86216695076366419584761488067220228053256612755484114208646435887019968055771
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3401.459288 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3401.459288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:820) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.33814498850756597827077195655457374242687722818964016768267003246128167013501
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 27207.720335 us: (chip_sw_base_vseq.sv:820) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
  UVM_INFO @ 27207.720335 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80443) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.4318803739267660402662676544797653119496944175711245381973587317743406497688
Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4598.976856 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80443) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4598.976856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.53805253312873386724485276178634727271904271027019484660707959391134805265289
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11247.377888 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11247.377888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.75838687670135586332968089520643006693734571512752682589391723259317614633351
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34904.471641 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34904.471641 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.96340990909361538795639885201344396441366475657428690072281590585570217328241
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3191.439800 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3191.439800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.35316747141693517267093847577258779193137771721431166524279427743843645456660
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2936.196264 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2936.196264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.3683949009437277147577158783024358711431536638445829202500945989724895685081
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2441.196875 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2441.196875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33125) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.35283620744470240736283749244442791818899262891779550430157786162078188196654
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2444.944516 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33125) { a_addr: 'h1047c  a_data: 'h5c28ddb6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h19956  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2444.944516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.90840596213938198710076055734907152115557323024778620854470306587918477212592
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2525.082490 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2525.082490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.83775260361984971162266969409450827819073476901744154105695915340908391601725
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3249.503500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3249.503500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.21870637028928758381072497461221891233512309989334267754584552554610475791339
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2647.000000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2647.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.60446292325462823778596717028987674496475894512030450410841133977582493202733
    Line 441, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3853.004882 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3853.004882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.106521769113976435054638499684957727143443185654554298941807502564132600327288
    Line 550, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.27968444957096393519728598147267990479310663132829432047601035378523123843349
    Line 570, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.62558892998221874612630959555925385417280258127052339769670775309081847556096
    Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 2990.796310 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 2990.796310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```