ADC_CTRL Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.270s	5.633ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.200s	712.870us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.530s	522.176us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	11.840s	26.896ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.280s	1.123ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.640s	436.315us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.530s	522.176us	1	1	100.00
		adc_ctrl_csr_aliasing	2.280s	1.123ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.350m	329.528ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.525m	164.631ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	12.961m	494.600ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	6.263m	481.283ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	9.013m	631.450ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	3.218m	193.394ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	5.103m	161.822ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.688m	395.863ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.030s	3.287ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	41.340s	27.951ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.766m	131.219ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	9.710m	372.432ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	0.920s	591.129us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.510s	477.868us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.470s	497.042us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.470s	497.042us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.200s	712.870us	1	1	100.00
		adc_ctrl_csr_rw	1.530s	522.176us	1	1	100.00
		adc_ctrl_csr_aliasing	2.280s	1.123ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.730s	4.915ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.200s	712.870us	1	1	100.00
		adc_ctrl_csr_rw	1.530s	522.176us	1	1	100.00
		adc_ctrl_csr_aliasing	2.280s	1.123ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.730s	4.915ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.430s	4.217ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.910s	4.336ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.910s	4.336ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.970s	3.541ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00