EDN Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.940s 29.167us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.780s 16.824us 1 1 100.00
V1 csr_rw edn_csr_rw 0.830s 18.222us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.050s 358.286us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.950s 36.622us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.210s 84.443us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.830s 18.222us 1 1 100.00
edn_csr_aliasing 0.950s 36.622us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.280s 78.246us 1 1 100.00
V2 csrng_commands edn_genbits 1.280s 78.246us 1 1 100.00
V2 genbits edn_genbits 1.280s 78.246us 1 1 100.00
V2 interrupts edn_intr 0.810s 42.551us 1 1 100.00
V2 alerts edn_alert 0.950s 43.857us 1 1 100.00
V2 errs edn_err 0.840s 18.366us 1 1 100.00
V2 disable edn_disable 0.750s 36.363us 1 1 100.00
edn_disable_auto_req_mode 0.920s 33.559us 1 1 100.00
V2 stress_all edn_stress_all 2.240s 136.554us 1 1 100.00
V2 intr_test edn_intr_test 0.710s 23.222us 1 1 100.00
V2 alert_test edn_alert_test 0.800s 39.621us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.990s 220.131us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.990s 220.131us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.780s 16.824us 1 1 100.00
edn_csr_rw 0.830s 18.222us 1 1 100.00
edn_csr_aliasing 0.950s 36.622us 1 1 100.00
edn_same_csr_outstanding 1.180s 50.764us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.780s 16.824us 1 1 100.00
edn_csr_rw 0.830s 18.222us 1 1 100.00
edn_csr_aliasing 0.950s 36.622us 1 1 100.00
edn_same_csr_outstanding 1.180s 50.764us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 3.460s 314.299us 1 1 100.00
edn_tl_intg_err 1.780s 92.870us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.860s 14.426us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.950s 43.857us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 3.460s 314.299us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 3.460s 314.299us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 3.460s 314.299us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 3.460s 314.299us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.950s 43.857us 1 1 100.00
edn_sec_cm 3.460s 314.299us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.950s 43.857us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.780s 92.870us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets