HMAC Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.980s 285.957us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.780s 20.324us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.670s 46.030us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.260s 322.733us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.150s 443.728us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.150s 149.770us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.670s 46.030us 1 1 100.00
hmac_csr_aliasing 4.150s 443.728us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 38.910s 8.799ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.013m 1.657ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.880s 186.584us 1 1 100.00
hmac_test_sha384_vectors 20.400s 985.434us 1 1 100.00
hmac_test_sha512_vectors 6.314m 22.844ms 1 1 100.00
hmac_test_hmac256_vectors 8.500s 3.023ms 1 1 100.00
hmac_test_hmac384_vectors 8.730s 309.254us 1 1 100.00
hmac_test_hmac512_vectors 10.880s 1.263ms 1 1 100.00
V2 burst_wr hmac_burst_wr 17.570s 1.298ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 54.550s 847.999us 1 1 100.00
V2 error hmac_error 8.180s 539.035us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.161m 2.255ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.980s 285.957us 1 1 100.00
hmac_long_msg 38.910s 8.799ms 1 1 100.00
hmac_back_pressure 1.013m 1.657ms 1 1 100.00
hmac_datapath_stress 54.550s 847.999us 1 1 100.00
hmac_burst_wr 17.570s 1.298ms 1 1 100.00
hmac_stress_all 7.880m 102.925ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.980s 285.957us 1 1 100.00
hmac_long_msg 38.910s 8.799ms 1 1 100.00
hmac_back_pressure 1.013m 1.657ms 1 1 100.00
hmac_datapath_stress 54.550s 847.999us 1 1 100.00
hmac_wipe_secret 1.161m 2.255ms 1 1 100.00
hmac_test_sha256_vectors 7.880s 186.584us 1 1 100.00
hmac_test_sha384_vectors 20.400s 985.434us 1 1 100.00
hmac_test_sha512_vectors 6.314m 22.844ms 1 1 100.00
hmac_test_hmac256_vectors 8.500s 3.023ms 1 1 100.00
hmac_test_hmac384_vectors 8.730s 309.254us 1 1 100.00
hmac_test_hmac512_vectors 10.880s 1.263ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.980s 285.957us 1 1 100.00
hmac_long_msg 38.910s 8.799ms 1 1 100.00
hmac_back_pressure 1.013m 1.657ms 1 1 100.00
hmac_datapath_stress 54.550s 847.999us 1 1 100.00
hmac_burst_wr 17.570s 1.298ms 1 1 100.00
hmac_error 8.180s 539.035us 1 1 100.00
hmac_wipe_secret 1.161m 2.255ms 1 1 100.00
hmac_test_sha256_vectors 7.880s 186.584us 1 1 100.00
hmac_test_sha384_vectors 20.400s 985.434us 1 1 100.00
hmac_test_sha512_vectors 6.314m 22.844ms 1 1 100.00
hmac_test_hmac256_vectors 8.500s 3.023ms 1 1 100.00
hmac_test_hmac384_vectors 8.730s 309.254us 1 1 100.00
hmac_test_hmac512_vectors 10.880s 1.263ms 1 1 100.00
hmac_stress_all 7.880m 102.925ms 1 1 100.00
V2 stress_all hmac_stress_all 7.880m 102.925ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 48.877us 1 1 100.00
V2 intr_test hmac_intr_test 0.570s 14.370us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.130s 56.459us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.130s 56.459us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.780s 20.324us 1 1 100.00
hmac_csr_rw 0.670s 46.030us 1 1 100.00
hmac_csr_aliasing 4.150s 443.728us 1 1 100.00
hmac_same_csr_outstanding 2.300s 719.036us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.780s 20.324us 1 1 100.00
hmac_csr_rw 0.670s 46.030us 1 1 100.00
hmac_csr_aliasing 4.150s 443.728us 1 1 100.00
hmac_same_csr_outstanding 2.300s 719.036us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.010s 118.469us 1 1 100.00
hmac_tl_intg_err 1.610s 79.868us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.610s 79.868us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.980s 285.957us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.820s 340.613us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 9.059m 25.234ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.770s 360.448us 1 1 100.00
TOTAL 28 28 100.00