I2C Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	16.160s	2.233ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.620s	2.782ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.850s	21.558us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.960s	48.688us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.250s	242.727us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.110s	437.888us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.110s	91.166us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.960s	48.688us	1	1	100.00
		i2c_csr_aliasing	2.110s	437.888us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.740s	19.286us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.070s	26.192us	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.819m	5.169ms	1	1	100.00
V2	host_override	i2c_host_override	0.650s	30.583us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.168m	15.716ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.323m	1.980ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.300s	261.221us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.720s	628.286us	1	1	100.00
		i2c_host_fifo_reset_rx	2.810s	132.597us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	34.830s	12.001ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.950s	1.249ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.870s	216.965us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.160s	524.704us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	3.688m	106.812ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.280s	1.273ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.790s	421.430us	1	1	100.00
		i2c_target_intr_smoke	4.870s	3.074ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.250s	722.060us	1	1	100.00
		i2c_target_fifo_reset_tx	0.940s	232.669us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	48.690s	52.134ms	1	1	100.00
		i2c_target_stress_rd	5.790s	421.430us	1	1	100.00
		i2c_target_intr_stress_wr	4.086m	23.052ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.610s	1.176ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.110s	10.046ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	3.730s	1.808ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	17.910s	10.059ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.710s	358.687us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.430s	489.508us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.819m	5.169ms	1	1	100.00
		i2c_host_perf_precise	3.462m	24.260ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.950s	1.249ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.820s	85.437us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.350s	1.629ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.850s	1.044ms	1	1	100.00
		i2c_target_nack_txstretch	1.080s	140.776us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.610s	808.353us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.060s	1.020ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.710s	24.682us	1	1	100.00
V2	intr_test	i2c_intr_test	0.950s	48.681us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.640s	272.450us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.640s	272.450us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.850s	21.558us	1	1	100.00
		i2c_csr_rw	0.960s	48.688us	1	1	100.00
		i2c_csr_aliasing	2.110s	437.888us	1	1	100.00
		i2c_same_csr_outstanding	1.030s	62.771us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.850s	21.558us	1	1	100.00
		i2c_csr_rw	0.960s	48.688us	1	1	100.00
		i2c_csr_aliasing	2.110s	437.888us	1	1	100.00
		i2c_same_csr_outstanding	1.030s	62.771us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.780s	156.034us	1	1	100.00
		i2c_sec_cm	0.960s	72.381us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.780s	156.034us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	12.400s	705.209us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.560s	678.840us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.700s	1.083ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.105816386711176876831236320615174444456771597961528362988016884078092988582665
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  19285941 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  19285941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.11162475624106751487915209974382316937328727245963908590587443726063078345439
      Line 97, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @  26192263 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  26192263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.31177355312320961520425707944414366439010280470055923887431590562579820148772
      Line 109, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 705209233 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 705209233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.105439779458623259563065188769509034673024417252930784228506747310840937174542
      Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1083452079 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1083452079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.97341891898528429379413765299057615553442021545668703174529618749089443966703
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 524704300 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 524704300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:

  • Test i2c_target_stretch has 1 failures.

    • 0.i2c_target_stretch.20381674682339663794181146580392861006210959739173558971758579813095223648879
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log

        UVM_FATAL @ 10046019124 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
        UVM_INFO @ 10046019124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.45226702955252967683498658685778585645875216485832212807646068302509213749585
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 678840232 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 121 [0x79])
        UVM_INFO @ 678840232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.93007393926234217844628984506171829545156129956389108824153644719931019085861
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10058802649 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10058802649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.74946880261401764100331283745803000450360961662519195486599816803948445161166
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 140776280 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 140776280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---