KEYMGR Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.130s	92.448us	1	1	100.00
V1	random	keymgr_random	1.990s	34.506us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.930s	44.888us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.890s	30.905us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	8.800s	1.800ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.560s	858.002us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.250s	20.981us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.890s	30.905us	1	1	100.00
		keymgr_csr_aliasing	4.560s	858.002us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.610s	182.451us	1	1	100.00
V2	sideload	keymgr_sideload	3.290s	401.631us	1	1	100.00
		keymgr_sideload_kmac	2.030s	43.278us	1	1	100.00
		keymgr_sideload_aes	2.100s	194.991us	1	1	100.00
		keymgr_sideload_otbn	3.190s	105.653us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.250s	236.659us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.190s	81.810us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.850s	134.807us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	6.600s	552.422us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.320s	252.922us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.670s	121.836us	1	1	100.00
V2	stress_all	keymgr_stress_all	3.260s	151.341us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.690s	10.477us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.930s	17.701us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.490s	528.996us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.490s	528.996us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.930s	44.888us	1	1	100.00
		keymgr_csr_rw	0.890s	30.905us	1	1	100.00
		keymgr_csr_aliasing	4.560s	858.002us	1	1	100.00
		keymgr_same_csr_outstanding	1.850s	34.415us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.930s	44.888us	1	1	100.00
		keymgr_csr_rw	0.890s	30.905us	1	1	100.00
		keymgr_csr_aliasing	4.560s	858.002us	1	1	100.00
		keymgr_same_csr_outstanding	1.850s	34.415us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
		keymgr_tl_intg_err	3.600s	354.301us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.990s	200.861us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.990s	200.861us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.990s	200.861us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.990s	200.861us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.290s	261.261us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.600s	354.301us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.990s	200.861us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.610s	182.451us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.990s	34.506us	1	1	100.00
		keymgr_csr_rw	0.890s	30.905us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.990s	34.506us	1	1	100.00
		keymgr_csr_rw	0.890s	30.905us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.990s	34.506us	1	1	100.00
		keymgr_csr_rw	0.890s	30.905us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.190s	81.810us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.320s	252.922us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.320s	252.922us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.990s	34.506us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.860s	135.571us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.400s	153.770us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.190s	81.810us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.400s	153.770us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.400s	153.770us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.400s	153.770us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	20.940s	1.303ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.400s	153.770us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	16.100s	5.828ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	30	100.00