KMAC/UNMASKED Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	3.150s	1.170ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.000s	37.493us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.260s	28.663us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.210s	297.465us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.470s	204.206us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.280s	57.069us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	28.663us	1	1	100.00
		kmac_csr_aliasing	3.470s	204.206us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.830s	12.355us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.830s	147.315us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	37.001m	98.102ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.614m	60.787ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.000s	3.677ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.540m	248.925ms	1	1	100.00
		kmac_test_vectors_sha3_384	14.632m	13.265ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.010s	1.453ms	1	1	100.00
		kmac_test_vectors_shake_128	2.395m	19.151ms	1	1	100.00
		kmac_test_vectors_shake_256	1.196m	1.579ms	1	1	100.00
		kmac_test_vectors_kmac	2.140s	141.076us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.810s	98.625us	1	1	100.00
V2	sideload	kmac_sideload	2.715m	24.956ms	1	1	100.00
V2	app	kmac_app	3.843m	122.695ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	40.600s	6.874ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.230s	41.689us	1	1	100.00
V2	error	kmac_error	1.169m	4.787ms	1	1	100.00
V2	key_error	kmac_key_error	1.610s	928.908us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.909m	10.052ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	12.310s	359.362us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	22.190s	331.751us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.120s	53.154us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.400s	63.818us	1	1	100.00
V2	stress_all	kmac_stress_all	21.371m	109.306ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.030s	21.086us	1	1	100.00
V2	alert_test	kmac_alert_test	1.040s	29.748us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.350s	178.087us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.350s	178.087us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.000s	37.493us	1	1	100.00
		kmac_csr_rw	1.260s	28.663us	1	1	100.00
		kmac_csr_aliasing	3.470s	204.206us	1	1	100.00
		kmac_same_csr_outstanding	1.740s	49.419us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.000s	37.493us	1	1	100.00
		kmac_csr_rw	1.260s	28.663us	1	1	100.00
		kmac_csr_aliasing	3.470s	204.206us	1	1	100.00
		kmac_same_csr_outstanding	1.740s	49.419us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.350s	147.333us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.350s	147.333us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.350s	147.333us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.350s	147.333us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.350s	183.738us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	20.570s	7.909ms	1	1	100.00
		kmac_tl_intg_err	3.340s	373.880us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.340s	373.880us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.400s	63.818us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	3.150s	1.170ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.715m	24.956ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.350s	147.333us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	20.570s	7.909ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	20.570s	7.909ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	20.570s	7.909ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	3.150s	1.170ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.400s	63.818us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	20.570s	7.909ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.279m	4.845ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	3.150s	1.170ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.618m	16.277ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.23419058420125669542099684438863357024107224469050496258324351462801613473985
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10052296812 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb3410000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10052296812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---