PATTGEN Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	72.015us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	14.957us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	49.502us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	144.230us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	21.852us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	61.129us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	49.502us	1	1	100.00
		pattgen_csr_aliasing	3.000s	21.852us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	12.000s	9.430ms	1	1	100.00
V2	error	pattgen_error	2.000s	56.868us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	3.000s	46.919us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	27.029us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	164.142us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	164.142us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	14.957us	1	1	100.00
		pattgen_csr_rw	2.000s	49.502us	1	1	100.00
		pattgen_csr_aliasing	3.000s	21.852us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	20.003us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	14.957us	1	1	100.00
		pattgen_csr_rw	2.000s	49.502us	1	1	100.00
		pattgen_csr_aliasing	3.000s	21.852us	1	1	100.00
		pattgen_same_csr_outstanding	2.000s	20.003us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	204.370us	1	1	100.00
		pattgen_sec_cm	2.000s	34.185us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	204.370us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	24.000s	2.689ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	551.924us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

• Job timed out after * minutes has 2 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.99347501587674096104746396841673548864989686501498317617484265136407699219296
      Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        Job timed out after 60 minutes
      

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.1067580216071304882330131808069290652969773634806938659656992735481660146048
      Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.108367457686121496321904525835226926067624063130410378117176414548295117436982
      Line 143, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 860846560 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 860848942 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 860848942 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 2/5
        UVM_INFO @ 860891046 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]