ROM_CTRL/64KB Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	10.660s	1.040ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.880s	393.347us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.830s	1.340ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.030s	207.369us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.930s	207.783us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.170s	1.090ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.830s	1.340ms	1	1	100.00
		rom_ctrl_csr_aliasing	5.930s	207.783us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.340s	297.755us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.800s	991.280us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.620s	304.927us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	20.240s	579.223us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.600s	408.662us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	7.350s	655.865us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.800s	728.451us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.800s	728.451us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.880s	393.347us	1	1	100.00
		rom_ctrl_csr_rw	6.830s	1.340ms	1	1	100.00
		rom_ctrl_csr_aliasing	5.930s	207.783us	1	1	100.00
		rom_ctrl_same_csr_outstanding	7.300s	2.088ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.880s	393.347us	1	1	100.00
		rom_ctrl_csr_rw	6.830s	1.340ms	1	1	100.00
		rom_ctrl_csr_aliasing	5.930s	207.783us	1	1	100.00
		rom_ctrl_same_csr_outstanding	7.300s	2.088ms	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	35.480s	5.728ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	7.053m	1.354ms	0	1	0.00
		rom_ctrl_tl_intg_err	48.380s	1.872ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	7.053m	1.354ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	7.053m	1.354ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	7.053m	1.354ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	7.053m	1.354ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	10.660s	1.040ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	10.660s	1.040ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	10.660s	1.040ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	48.380s	1.872ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
		rom_ctrl_kmac_err_chk	14.600s	408.662us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.488m	9.534ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	35.480s	5.728ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	7.053m	1.354ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.398m	1.804ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.30903132323503067669982404979881942430259342389331740301352507432969779877457
      Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 2168518ps failed at 2168518ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 289: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 2188926ps failed at 2188926ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'