| V1 |
random |
rv_timer_random |
0.630s |
11.737us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
0.710s |
26.405us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
0.620s |
15.236us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
1.760s |
241.728us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
0.890s |
35.223us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
0.750s |
16.265us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
0.620s |
15.236us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.890s |
35.223us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
0.690s |
185.966us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.840s |
1.252ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
6.060s |
40.006ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
6.060s |
40.006ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
1.750s |
3.794ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
0.670s |
37.581us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
0.690s |
14.172us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
1.640s |
395.989us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
1.640s |
395.989us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
0.710s |
26.405us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.620s |
15.236us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.890s |
35.223us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.780s |
61.564us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
0.710s |
26.405us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.620s |
15.236us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.890s |
35.223us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.780s |
61.564us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
0.950s |
359.615us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
0.930s |
284.280us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
0.930s |
284.280us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
0.540s |
47.716us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
0.530s |
32.036us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
38.900s |
9.813ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |