SPI_DEVICE/1R1W Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.400s	3.920ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.100s	23.089us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.510s	73.816us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.660s	7.460ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.140s	212.164us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.410s	50.116us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.510s	73.816us	1	1	100.00
		spi_device_csr_aliasing	5.140s	212.164us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	17.661us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.620s	56.497us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.810s	16.177us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.680s	3.557us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	4.766us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.830s	24.020us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.830s	24.020us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.570s	2.494ms	1	1	100.00
		spi_device_tpm_sts_read	0.720s	68.135us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.280s	3.808ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.780s	412.241us	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	10.180s	52.925ms	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	10.180s	52.925ms	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.050s	415.223us	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.050s	415.223us	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.050s	415.223us	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.050s	415.223us	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.050s	415.223us	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.990s	201.984us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	18.050s	8.293ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	18.050s	8.293ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	18.050s	8.293ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.610s	1.570ms	1	1	100.00
		spi_device_read_buffer_direct	10.240s	1.574ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	18.050s	8.293ms	1	1	100.00
		spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.355m	44.074ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.750s	4.112ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.750s	4.112ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.400s	3.920ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.135m	82.853ms	1	1	100.00
V2	stress_all	spi_device_stress_all	32.120s	5.482ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.870s	17.585us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.700s	28.527us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.880s	560.130us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.880s	560.130us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.100s	23.089us	1	1	100.00
		spi_device_csr_rw	1.510s	73.816us	1	1	100.00
		spi_device_csr_aliasing	5.140s	212.164us	1	1	100.00
		spi_device_same_csr_outstanding	2.860s	383.282us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.100s	23.089us	1	1	100.00
		spi_device_csr_rw	1.510s	73.816us	1	1	100.00
		spi_device_csr_aliasing	5.140s	212.164us	1	1	100.00
		spi_device_same_csr_outstanding	2.860s	383.282us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.110s	227.731us	1	1	100.00
		spi_device_tl_intg_err	10.980s	579.700us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.980s	579.700us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	0.850s	132.441us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.40760228388748625946660015537197672129848458300573860987586402556534493088786
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2976655 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[53])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2976655 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2976655 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[949])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.84138096902460094146576088826682738804542837357965305840349723156365053141926
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2318069 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x152458 [101010010010001011000] vs 0x0 [0])
        UVM_ERROR @   2404069 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf8917 [11111000100100010111] vs 0x0 [0])
        UVM_ERROR @   2408069 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb3428d [101100110100001010001101] vs 0x0 [0])
        UVM_ERROR @   2410069 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7b41bf [11110110100000110111111] vs 0x0 [0])
        UVM_ERROR @   2478069 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7fb720 [11111111011011100100000] vs 0x0 [0])