SPI_DEVICE/2P Simulation Results

Thursday September 11 2025 19:16:40 UTC

GitHub Revision: ba7ffa6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.060m	30.165ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.090s	18.957us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.300s	50.173us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.080s	921.522us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.150s	109.092us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.180s	360.224us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.300s	50.173us	1	1	100.00
		spi_device_csr_aliasing	5.150s	109.092us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	13.857us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.410s	120.128us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.810s	37.573us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.080s	15.532us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.840s	39.051us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.510s	772.904us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.510s	772.904us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.180s	1.795ms	1	1	100.00
		spi_device_tpm_sts_read	1.200s	322.380us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.890s	10.055ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.290s	260.215us	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	9.600s	6.345ms	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	9.600s	6.345ms	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.380s	210.084us	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.380s	210.084us	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.380s	210.084us	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.380s	210.084us	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.380s	210.084us	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	20.710s	39.116ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	14.320s	3.043ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	14.320s	3.043ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	14.320s	3.043ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.020s	106.370us	1	1	100.00
		spi_device_read_buffer_direct	7.670s	28.489ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	14.320s	3.043ms	1	1	100.00
		spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.069m	22.993ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.480s	569.061us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.480s	569.061us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.060m	30.165ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.720s	2.323ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.818m	37.873ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.000s	27.609us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.660s	20.121us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.710s	134.494us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.710s	134.494us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.090s	18.957us	1	1	100.00
		spi_device_csr_rw	1.300s	50.173us	1	1	100.00
		spi_device_csr_aliasing	5.150s	109.092us	1	1	100.00
		spi_device_same_csr_outstanding	3.350s	225.230us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.090s	18.957us	1	1	100.00
		spi_device_csr_rw	1.300s	50.173us	1	1	100.00
		spi_device_csr_aliasing	5.150s	109.092us	1	1	100.00
		spi_device_same_csr_outstanding	3.350s	225.230us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.020s	122.668us	1	1	100.00
		spi_device_tl_intg_err	12.540s	643.892us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.540s	643.892us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	32.060s	14.889ms	1	1	100.00
		TOTAL			33	33	100.00